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Cadence
Cadence

Leading company in the technology industry

Performance Architect

职能后端
级别中级
地点AUSTIN
方式现场办公
类型全职
发布1周前
立即申请

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.Performance Architect Location

Austin, TX

Role Overview

We are seeking a Performance Architect to drive system‑level performance architecture for ARM‑based So Cs and chiplet platforms. In this role, you will define, analyze, and optimize performance across CPUs, interconnect, memory subsystems, and accelerators, working closely with system architects, IP teams, design, and software.

This is a senior technical role requiring deep expertise in ARM architectures,memory systems, and end‑to‑end performance modeling, with the ability to influence architecture decisions early and guide teams through implementation and validation.

Key Responsibilities System & SoC Performance Architecture

  • Define performance requirements, KPIs, and budgets across CPU, interconnect, memory, and I/O subsystems.
  • Drive architectural trade‑offs involving latency, bandwidth, throughput, power, and area.
  • Evaluate and optimize performance for heterogeneous workloads (NPU/AI, ISP, VISION, I/O).

Interconnect & Chiplet Performance

  • Evaluate and optimize NoC / fabric architectures (latency, bandwidth, congestion, QoS).
  • Analyze performance impacts of chiplet partitioning, die‑to‑die interconnects (e.g., UCIe‑class links), and protocol overheads.
  • Identify bottlenecks across chiplet boundaries and propose architectural mitigations.

Performance Modeling & Analysis

  • Build and maintain system‑level performance models (transaction‑level, analytical, or cycle‑approximate).
  • Perform workload‑driven studies using synthetic traffic, benchmarks, and real software traces.
  • Correlate model results with RTL, emulation, or silicon data as designs mature.
  • Clearly communicate performance findings and recommendations to cross‑functional teams.

Cross‑Functional Leadership

  • Work closely with system architects, IP architects, design, verification, and software teams.
  • Provide technical leadership and mentorship on performance topics.
  • Influence architectural decisions through data‑driven analysis and clear technical communication.

Required Qualifications Experience

  • 10+ years of experience in SoC, system, or performance architecture (staff‑level expectations).
  • Proven experience working on ARM‑based systems in data center, automotive, mobile, or embedded domains.

Technical Expertise

  • Deep understanding of computer architecture:
  • Memory hierarchy and bandwidth/latency trade‑offs
  • Strong knowledge of ARM architecture and ecosystem:
  • ARMv8/ARMv9 CPUs
  • Performance monitoring (PMU/AMU)
  • System memory management concepts (SMMU, TLBs, page tables)
  • Solid understanding of interconnects and fabrics (NoC, coherency protocols, QoS).
  • Experience with performance modeling and analysis techniques

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关于Cadence

Cadence

Cadence

Public

Cadence Design Systems, Inc. is an American multinational technology and computational software company headquartered in San Jose, California.

5,001-10,000

员工数

San Jose

总部位置

$8.5B

企业估值

评价

10条评价

3.9

10条评价

工作生活平衡

3.8

薪酬

2.7

企业文化

4.2

职业发展

3.2

管理层

2.8

72%

推荐率

优点

Flexible work arrangements and remote options

Great company culture and collaborative team

Good benefits and job security

缺点

Below average compensation and salary

High workload and overwhelming at times

Limited career advancement opportunities

薪资范围

75个数据点

Junior/L3

Junior/L3 · Data Analyst

1份报告

$91,103

年薪总额

基本工资

$85,276

股票

-

奖金

$5,827

$59,612

$139,984

面试评价

1条评价

难度

3.0

/ 5

时长

14-28周

面试流程

1

Application Review

2

Recruiter Screen

3

Technical Phone Screen

4

Onsite/Virtual Interviews

5

Final Decision

常见问题

Technical Knowledge

Behavioral/STAR

Past Experience

Problem Solving