招聘
必备技能
Parasitic extraction
Transistor-level extraction
Cell-level extraction
Analog design
Physical verification
Simulation
RC correlation
Communication
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Job Description
The Product Engineering team collaborates closely with customers, foundries, R&D, Marketing, and Application Engineers to develop solutions that address our customers’ unique and complex design challenges. We are seeking a PEX (RC Parasitic Extraction) Product Engineer to support foundry design enablement kits and to deliver Cadence PEX tool solutions in a timely and professional manner. The candidate will work both on-site and off-site.
Key Responsibilities:
- Act as the primary interface between customers and corporate R&D for all PEX‑related issues.
- Develop extraction Techfiles for strategic partners.
- Evaluate and qualify extraction Techfiles using provided testcases.
- Establish efficient flows to improve PEX tool quality and product performance.
- Execute expert-level benchmarks and resolve complex customer issues.
- Collaborate with R&D, field teams, customers, and foundries to define product requirements and enhancements.
- Work closely with headquarters R&D and Product Engineers across global sites to resolve technical issues.
Requirements
- 9+ years of Extraction experience with Bachelor’s degree in electrical engineering is required, Master’s degree is preferred.
- Strong background in transistor-level and cell-level parasitic extraction, with solid understanding of cell-level and analog design.
- Hands-on experience with industry PEX tools such as StarRC or QRC.
- Experience with extraction in advanced technology nodes.
- Knowledge and experience with physical verification tools (e.g., PVS/Pegasus, Calibre, ICV) required.
- Knowledge and experience with Simulator tools (e.g., HSPICE, Spectre..)
- Knowledge of RC correlation and delay on design data.
- Good communication skills internally with team members and externally with customers.
- Work experience in-design service team would be advantageous.
- Proficiency in spoken and written English.
- Programming experience in Tcl, Perl, Python, or SKILL is a plus
We’re doing work that matters. Help us solve what others can’t.
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关于Cadence

Cadence
PublicCadence Design Systems provides electronic design automation (EDA) software, hardware, and IP for designing and verifying electronic systems and semiconductors.
5,001-10,000
员工数
San Jose
总部位置
$8.5B
企业估值
评价
4.0
10条评价
工作生活平衡
4.2
薪酬
2.8
企业文化
4.1
职业发展
3.2
管理层
3.4
72%
推荐给朋友
优点
Good work-life balance
Supportive and collaborative team environment
Flexible work arrangements
缺点
Below market compensation
Limited career advancement opportunities
Heavy workload and long hours
薪资范围
58个数据点
Junior/L3
Junior/L3 · Data Analyst
1份报告
$91,103
年薪总额
基本工资
$85,276
股票
-
奖金
$5,827
$59,612
$139,984
面试经验
1次面试
难度
3.0
/ 5
时长
14-28周
面试流程
1
Application Review
2
Recruiter Screen
3
Technical Phone Screen
4
Onsite/Virtual Interviews
5
Final Decision
常见问题
Technical Knowledge
Behavioral/STAR
Past Experience
Problem Solving
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