refresh

트렌딩 기업

트렌딩

채용

JobsCadence

Application Engineer II: Silicon Signoff and Verification

Cadence

Application Engineer II: Silicon Signoff and Verification

Cadence

BELO HORIZONTE

·

On-site

·

Full-time

·

2w ago

Benefits & Perks

Competitive benefits

Required Skills

MOS transistors

Physical verification

DRC

LVS

Parasitic extraction

IR Drop analysis

Electromigration

Tcl

Perl

Python

Communication

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence Design Systems Inc. is looking for a motivated

Application Engineer II: Silicon Signoff and Verificationcandidate to work with us in Belo Horizonte, Brazil

**.At Cadence, we hire and develop leaders and innovators who want to impact the world of technology. Cadence has been nominated as a Great Place to Work globally and in Brazil and is also a Fortune 100 Best Companies to Work For.

As a

Senior Application Engineering:

  • Silicon Signoff and Verification **member, you will be part of the **Silicon Signoff and Verification (SSV)team.

The SSV team works with the Quantus,Pegasus and Voltus platforms.

To understand more on what we do, you can visit here.

Job Description:

  • Helping customers to adopt and proliferate our IC Signoff solutions
  • Conducting technical presentations, technical training, and product demonstrations, including development of customized presentations
  • Supporting technical evaluations and benchmarks
  • Help R&D and product engineers develop competitive and creative technical solutions

Requirements:

  • Complete Bachelors in Electrical, Electronics, System Engineering, computer science or related areas
  • MOS transistors, Physical verification flows ( i.e.. DRC, LVS & FILL), Parasitic extraction flows, IR Drop/Electromigration tools, Physical verification rule writing.
  • Excellent written and verbal communication skills
  • Interest in learning new technologies
  • Open to continued personal development to meet the evolving demands of the EDA industry
  • Experience in scripting languages such as Tcl/Perl/Python is a must
  • Team player with a positive attitude, willingness to offer and execute ideas and solutions to enhance processes within an evolving environment

Nice to have:

  • Industry Physical Design experience
  • Prior experience with IC digital implementation flows and font-end EDA tools including Synthesis, DFT, and Logical Equivalence Checking
  • Prior experience with Cadence tools such as Genus, Innovus, Conformal, Tempus, Modus, Voltus or ICC, ICC2, DC or Primetime is highly desired
  • Experience with advanced nodes

Additional Job Details:

  • Employment category: CLT
  • Employment term: 40 hours/week.
  • Competitive benefits.
  • Location: Av Contorno 5800, Belo Horizonte, Minas Gerais Brazil.

About Cadence Design Systems:

Cadence is the only company that provides the expertise and tools, IP, and hardware required for the entire electronics design chain, from chip design to chip packaging to boards and to systems. We enable electronic systems and semiconductor companies to create innovative products that transform the way people live, work, and play. Our products are used in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. For more information, access http://www.cadence.com.

We’re doing work that matters. Help us solve what others can’t.

Total Views

0

Apply Clicks

0

Mock Applicants

0

Scraps

0

About Cadence

Cadence

Cadence

Public

Cadence Design Systems provides electronic design automation (EDA) software, hardware, and IP for designing and verifying electronic systems and semiconductors.

5,001-10,000

Employees

San Jose

Headquarters

Reviews

3.3

7 reviews

Work Life Balance

2.0

Compensation

2.5

Culture

1.8

Career

2.0

Management

1.5

15%

Recommend to a Friend

Pros

Built strong client relationships

Useful for repetitive tasks

Employment opportunities

Cons

Poor management and micromanagement

Lack of career growth opportunities

Technical architecture and code quality issues

Salary Ranges

65 data points

Junior/L3

Junior/L3 · Data Analyst

1 reports

$91,103

total / year

Base

$85,276

Stock

-

Bonus

$5,827

$59,612

$139,984

Interview Experience

1 interviews

Difficulty

3.0

/ 5

Duration

14-28 weeks

Interview Process

1

Application Review

2

Recruiter Screen

3

Technical Phone Screen

4

Onsite/Virtual Interviews

5

Final Decision

Common Questions

Technical Knowledge

Behavioral/STAR

Past Experience

Problem Solving