採用
必須スキル
C++
Numerical analysis
VLSI circuit simulation
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
The Engineer is responsible for designing, implementing and maintaining software designed to perform transistor-level VLSI circuit simulation. The ideal candidate would have expertise in numerical techniques for VLSI circuit simulation. Understanding of analog/RF/custom IC design and verification practices is a strong plus. Candidate should have an advanced degree in electrical engineering, computer science, applied mathematics, or similar. Candidates with experience in related fields will be considered, particularly:
1. Numerical analysis, especially numerical linear algebra, sparse matrix techniques, or numerical methods for solution of ordinary differential equations;
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High performance computing (HPC) and performance critical applications;
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Including (but no limited) hardware-aware optimization, GPU, etc.
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Computational electromagnetics
Candidate should be proficient in C/C development. Demonstrated software engineering skills, with a good understanding of efficient implementation of high-performance numerical algorithms and associated data structure design, is a plus.
Candidate should have strong communications and interpersonal skills and be able to work as part of a geographically distributed development team.
The engineer should have ability to work with an engineering and cross-functional team to deliver innovative technologies in a production environment.
We’re doing work that matters. Help us solve what others can’t.
総閲覧数
0
応募クリック数
0
模擬応募者数
0
スクラップ
0
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Cadenceについて

Cadence
PublicCadence Design Systems provides electronic design automation (EDA) software, hardware, and IP for designing and verifying electronic systems and semiconductors.
5,001-10,000
従業員数
San Jose
本社所在地
$8.5B
企業価値
レビュー
4.0
10件のレビュー
ワークライフバランス
4.2
報酬
2.8
企業文化
4.1
キャリア
3.2
経営陣
3.4
72%
友人に勧める
良い点
Good work-life balance
Supportive and collaborative team environment
Flexible work arrangements
改善点
Below market compensation
Limited career advancement opportunities
Heavy workload and long hours
給与レンジ
58件のデータ
Junior/L3
Junior/L3 · Data Analyst
1件のレポート
$91,103
年収総額
基本給
$85,276
ストック
-
ボーナス
$5,827
$59,612
$139,984
面接体験
1件の面接
難易度
3.0
/ 5
期間
14-28週間
面接プロセス
1
Application Review
2
Recruiter Screen
3
Technical Phone Screen
4
Onsite/Virtual Interviews
5
Final Decision
よくある質問
Technical Knowledge
Behavioral/STAR
Past Experience
Problem Solving
ニュース&話題
Ninety One UK Ltd Cuts Position in Cadence Design Systems, Inc. $CDNS - MarketBeat
MarketBeat
News
·
4d ago
Moran Wealth Management LLC Sells 19,592 Shares of Cadence Design Systems, Inc. $CDNS - MarketBeat
MarketBeat
News
·
4d ago
Cadence Maps Its Future Beyond EDA With Agentic AI and Simulation - HPCwire
HPCwire
News
·
4d ago
Lesser-Known Cadence Design Systems Just Landed Google and Nvidia Deals. Should You Buy CDNS Stock? - Barchart.com
Barchart.com
News
·
5d ago