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Sr Principal Program Manager

Cadence

Sr Principal Program Manager

Cadence

BANGALORE

·

On-site

·

Full-time

·

1w ago

Required Skills

Project Management

Verilog/RTL coding

Verification

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Description Summary:

We are looking for a Principal Technical Program Manager who will be responsible for the overall coordination of R&D Development Projects and Key Customer Engagements within the Design IP Group. The candidate must have solid, hands-on experience with IP development and/or implementation in SoC with experience in successfully leading or managing IP or SOC designs. We are looking for an individual with good leadership skills and who takes ownership to ensure flawless execution. The person needs to be passionate who can seamlessly work with multiple functional teams, possesses clear communication skills and exhibits great ability to organize and structure the activities to ensure project success.

Job Description:

As a Program Manager you are responsible for driving the various IP development projects. You must be knowledgeable about IP design flow and be familiar with SOC design flow. You will be responsible for creating and executing project plan, proactively mitigating risks, and managing the Project life cycle from inception to project delivery and post-production support. You will also be responsible for managing external stakeholders including customers.

Responsibilities:

  • Work with internal & external customers, stakeholders to define project objectives and requirements.
  • Prioritize requirements and define scope to meet customer needs in a timely manner given available resources.
  • Develop, maintain, and distribute (as appropriate) standard project management deliverables for the successful implementation of the project, including: implementation plan, project schedule, project budget and variances, issues & action items log, meeting minutes, risks assessment and contingencies.
  • Manage deliverables (including SOWs, change management, approval of deliverables).
  • Partner with internal and external development teams to deliver on time and with the quality required.
  • Serve as the project owner in development process; maintaining quality checklists, Jira tickets, schedule tracker etc.
  • Anticipate problems and complications and formulate solutions so as not to impede the progress of the project.
  • Assume responsibility and drive ownership for issue resolution.
  • Holding status update meetings with technical teams and updating higher management on the project progress.
  • Create and maintain scorecards to track project performance.
  • Be accountable for on time project delivery, product quality, cost, and operations.

Qualifications:

  • Bachelor’s degree in engineering from an accredited institution.
  • 10+ years of experience out of which at least 2+ years of Program Management or Technical Product Management experience in Chip Design/ VLSI organization.
  • Knowledgeable about interface IP like DDR, HBM, etc is an added advantage
  • Strong project management skills with the ability to work on and track multiple projects simultaneously.
  • Demonstrated ability to think creatively and strategically when executing the project and solving problems.
  • Familiar with mixed-signal IP design flow and methodologies, Verilog/RTL coding & Verification
  • Excellent interpersonal skills and ability to communicate effectively with both technical and nontechnical individuals.

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About Cadence

Cadence

Cadence

Public

Cadence Design Systems provides electronic design automation (EDA) software, hardware, and IP for designing and verifying electronic systems and semiconductors.

5,001-10,000

Employees

San Jose

Headquarters

Reviews

3.3

7 reviews

Work Life Balance

2.0

Compensation

2.5

Culture

1.8

Career

2.0

Management

1.5

15%

Recommend to a Friend

Pros

Built strong client relationships

Useful for repetitive tasks

Employment opportunities

Cons

Poor management and micromanagement

Lack of career growth opportunities

Technical architecture and code quality issues

Salary Ranges

65 data points

Junior/L3

Junior/L3 · Data Analyst

1 reports

$91,103

total / year

Base

$85,276

Stock

-

Bonus

$5,827

$59,612

$139,984

Interview Experience

1 interviews

Difficulty

3.0

/ 5

Duration

14-28 weeks

Interview Process

1

Application Review

2

Recruiter Screen

3

Technical Phone Screen

4

Onsite/Virtual Interviews

5

Final Decision

Common Questions

Technical Knowledge

Behavioral/STAR

Past Experience

Problem Solving