
Leading company in the technology industry
Sr Principal Program Manager
필수 스킬
Project Management
Verilog/RTL coding
Verification
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Job Description Summary:
We are looking for a Principal Technical Program Manager who will be responsible for the overall coordination of R&D Development Projects and Key Customer Engagements within the Design IP Group. The candidate must have solid, hands-on experience with IP development and/or implementation in SoC with experience in successfully leading or managing IP or SOC designs. We are looking for an individual with good leadership skills and who takes ownership to ensure flawless execution. The person needs to be passionate who can seamlessly work with multiple functional teams, possesses clear communication skills and exhibits great ability to organize and structure the activities to ensure project success.
Job Description:
As a Program Manager you are responsible for driving the various IP development projects. You must be knowledgeable about IP design flow and be familiar with SOC design flow. You will be responsible for creating and executing project plan, proactively mitigating risks, and managing the Project life cycle from inception to project delivery and post-production support. You will also be responsible for managing external stakeholders including customers.
Responsibilities:
- Work with internal & external customers, stakeholders to define project objectives and requirements.
- Prioritize requirements and define scope to meet customer needs in a timely manner given available resources.
- Develop, maintain, and distribute (as appropriate) standard project management deliverables for the successful implementation of the project, including: implementation plan, project schedule, project budget and variances, issues & action items log, meeting minutes, risks assessment and contingencies.
- Manage deliverables (including SOWs, change management, approval of deliverables).
- Partner with internal and external development teams to deliver on time and with the quality required.
- Serve as the project owner in development process; maintaining quality checklists, Jira tickets, schedule tracker etc.
- Anticipate problems and complications and formulate solutions so as not to impede the progress of the project.
- Assume responsibility and drive ownership for issue resolution.
- Holding status update meetings with technical teams and updating higher management on the project progress.
- Create and maintain scorecards to track project performance.
- Be accountable for on time project delivery, product quality, cost, and operations.
Qualifications:
- Bachelor’s degree in engineering from an accredited institution.
- 10+ years of experience out of which at least 2+ years of Program Management or Technical Product Management experience in Chip Design/ VLSI organization.
- Knowledgeable about interface IP like DDR, HBM, etc is an added advantage
- Strong project management skills with the ability to work on and track multiple projects simultaneously.
- Demonstrated ability to think creatively and strategically when executing the project and solving problems.
- Familiar with mixed-signal IP design flow and methodologies, Verilog/RTL coding & Verification
- Excellent interpersonal skills and ability to communicate effectively with both technical and nontechnical individuals.
We’re doing work that matters. Help us solve what others can’t.
전체 조회수
0
전체 지원 클릭
0
전체 Mock Apply
0
전체 스크랩
0
비슷한 채용공고
Cadence 소개

Cadence
PublicCadence Design Systems, Inc. is an American multinational technology and computational software company headquartered in San Jose, California.
5,001-10,000
직원 수
San Jose
본사 위치
$8.5B
기업 가치
리뷰
10개 리뷰
3.9
10개 리뷰
워라밸
3.8
보상
2.7
문화
4.2
커리어
3.2
경영진
2.8
72%
지인 추천률
장점
Flexible work arrangements and remote options
Great company culture and collaborative team
Good benefits and job security
단점
Below average compensation and salary
High workload and overwhelming at times
Limited career advancement opportunities
연봉 정보
75개 데이터
Senior/L5
Director
Senior/L5 · AE Director
1개 리포트
$231,524
총 연봉
기본급
$201,323
주식
-
보너스
-
$231,524
$231,524
면접 후기
후기 1개
난이도
3.0
/ 5
소요 기간
14-28주
면접 과정
1
Application Review
2
Recruiter Screen
3
Technical Phone Screen
4
Onsite/Virtual Interviews
5
Final Decision
자주 나오는 질문
Technical Knowledge
Behavioral/STAR
Past Experience
Problem Solving
최근 소식
Cadence Design Systems, Inc. $CDNS Shares Bought by Mitsubishi UFJ Trust & Banking Corp - MarketBeat
MarketBeat
News
·
1w ago
Cadence Design Systems Rides AI Wave in Earnings - TipRanks
TipRanks
News
·
1w ago
Teen killed, older sister being taken off life support after crash - WSB-TV
WSB-TV
News
·
1w ago
Cadence lifts annual revenue forecast on sustained AI chip-design boom - Reuters
Reuters
News
·
1w ago



