
Leading company in the technology industry
Sr Principal Program Manager
必須スキル
Project Management
Verilog/RTL coding
Verification
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Job Description Summary:
We are looking for a Principal Technical Program Manager who will be responsible for the overall coordination of R&D Development Projects and Key Customer Engagements within the Design IP Group. The candidate must have solid, hands-on experience with IP development and/or implementation in SoC with experience in successfully leading or managing IP or SOC designs. We are looking for an individual with good leadership skills and who takes ownership to ensure flawless execution. The person needs to be passionate who can seamlessly work with multiple functional teams, possesses clear communication skills and exhibits great ability to organize and structure the activities to ensure project success.
Job Description:
As a Program Manager you are responsible for driving the various IP development projects. You must be knowledgeable about IP design flow and be familiar with SOC design flow. You will be responsible for creating and executing project plan, proactively mitigating risks, and managing the Project life cycle from inception to project delivery and post-production support. You will also be responsible for managing external stakeholders including customers.
Responsibilities:
- Work with internal & external customers, stakeholders to define project objectives and requirements.
- Prioritize requirements and define scope to meet customer needs in a timely manner given available resources.
- Develop, maintain, and distribute (as appropriate) standard project management deliverables for the successful implementation of the project, including: implementation plan, project schedule, project budget and variances, issues & action items log, meeting minutes, risks assessment and contingencies.
- Manage deliverables (including SOWs, change management, approval of deliverables).
- Partner with internal and external development teams to deliver on time and with the quality required.
- Serve as the project owner in development process; maintaining quality checklists, Jira tickets, schedule tracker etc.
- Anticipate problems and complications and formulate solutions so as not to impede the progress of the project.
- Assume responsibility and drive ownership for issue resolution.
- Holding status update meetings with technical teams and updating higher management on the project progress.
- Create and maintain scorecards to track project performance.
- Be accountable for on time project delivery, product quality, cost, and operations.
Qualifications:
- Bachelor’s degree in engineering from an accredited institution.
- 10+ years of experience out of which at least 2+ years of Program Management or Technical Product Management experience in Chip Design/ VLSI organization.
- Knowledgeable about interface IP like DDR, HBM, etc is an added advantage
- Strong project management skills with the ability to work on and track multiple projects simultaneously.
- Demonstrated ability to think creatively and strategically when executing the project and solving problems.
- Familiar with mixed-signal IP design flow and methodologies, Verilog/RTL coding & Verification
- Excellent interpersonal skills and ability to communicate effectively with both technical and nontechnical individuals.
We’re doing work that matters. Help us solve what others can’t.
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Cadenceについて

Cadence
PublicCadence Design Systems, Inc. is an American multinational technology and computational software company headquartered in San Jose, California.
5,001-10,000
従業員数
San Jose
本社所在地
$8.5B
企業価値
レビュー
10件のレビュー
3.9
10件のレビュー
ワークライフバランス
3.8
報酬
2.7
企業文化
4.2
キャリア
3.2
経営陣
2.8
72%
知人への推奨率
良い点
Flexible work arrangements and remote options
Great company culture and collaborative team
Good benefits and job security
改善点
Below average compensation and salary
High workload and overwhelming at times
Limited career advancement opportunities
給与レンジ
75件のデータ
Senior/L5
Director
Senior/L5 · AE Director
1件のレポート
$231,524
年収総額
基本給
$201,323
ストック
-
ボーナス
-
$231,524
$231,524
面接レビュー
レビュー1件
難易度
3.0
/ 5
期間
14-28週間
面接プロセス
1
Application Review
2
Recruiter Screen
3
Technical Phone Screen
4
Onsite/Virtual Interviews
5
Final Decision
よくある質問
Technical Knowledge
Behavioral/STAR
Past Experience
Problem Solving
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