포지션 소개
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
- IP Integration and release Engineer for SSG IP Release engineering team.
- Position is based in Bangalore.
- The role would include IP integration, verification, and release of the IP solution of Cadence to different customers.
- The work involved will be working with the existing RTL, integration of the PHY and controller to create the sub-system, addition of new features into the RTL, ensuring various customer configurations are clean as part of verification regressions, supporting customers, ensuring design is clean for LINT and CDC design guidelines.
- Proficient in ASIC development flows like Lint/CDC/Synthesis (preferably with Genus)/STA. Ability to debug and setup new flows.
Position Requirements:
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BE/BTech/ME/MTech
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Electrical / Electronics / VLSI with an experience as a design verification engineer, with a large portion of the recent work experience on RTL integration and verification.
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6-10 years of core RTL integration and verification experience using Verilog is a must.
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System Verilog experience and experience with UVM based environment usage / debugging is required.
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PCIe/CXL/IDE experience is highly desirable. Prior experience in implementation of complex protocols is a must.
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Prior experience in IP development teams would be an added advantage.
Scripting knowledge is an advantage.
We’re doing work that matters. Help us solve what others can’t.
필수 스킬
Design
