채용
필수 스킬
Physical design
Floorplan
CTS
STA
Physical verification
Power analysis
Perl
C shell
TCL
Makefile
Python
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
About the team:
Our team deliver many high-performance products based on the industry’s most advanced technology with high frequencies up to 8800MHz.
Our product processes include TSMC 2nm/3nm/5nm/7nm/12nm and Samsung 2nm/4nm/5nm/7nm/8nm/10nm, etc. In the team you will face great challenges such as FP, CTS, STA, etc. At the same time, you will get rich experience and advanced methodology.
Job Responsibilities:
Focus on high-speed digital DDR PHY IP physical implementation, develop necessary scripts or tools to enhance current PD design flow. Work in product projects, including but not limited to: complete the project tasks; solve design issue and provide flow to check and avoid similar issue; analyze and summarize PPA optimization methodologies and results, implement optimal design parameters and flows for different projects.
Job Requirement:
-BS with minimum 4 years of experience. MS with minimum 2 years of experience.
-Good physical design experience in the digital implementation domain including Floorplan, CTS, STA, Physical verification, Power analysis.
-Solid background in circuits, electronics, physics, be willing to learn new technology for cutting edge process node and advanced design methodology.
-Skilled in scripting language, such as Perl, C shell, TCL, Makefile, Python.
-Familiar with EDA tools like Innovus, ICC, Calibre, Tempus, Prime Time, etc.
We’re doing work that matters. Help us solve what others can’t.
총 조회수
1
총 지원 클릭 수
0
모의 지원자 수
0
스크랩
0
비슷한 채용공고
Cadence 소개

Cadence
PublicCadence Design Systems provides electronic design automation (EDA) software, hardware, and IP for designing and verifying electronic systems and semiconductors.
5,001-10,000
직원 수
San Jose
본사 위치
$8.5B
기업 가치
리뷰
4.0
10개 리뷰
워라밸
4.2
보상
2.8
문화
4.1
커리어
3.2
경영진
3.4
72%
친구에게 추천
장점
Good work-life balance
Supportive and collaborative team environment
Flexible work arrangements
단점
Below market compensation
Limited career advancement opportunities
Heavy workload and long hours
연봉 정보
58개 데이터
Mid/L4
Mid/L4 · Design Engineer
6개 리포트
$139,837
총 연봉
기본급
$124,197
주식
-
보너스
-
$110,434
$186,828
면접 경험
1개 면접
난이도
3.0
/ 5
소요 기간
14-28주
면접 과정
1
Application Review
2
Recruiter Screen
3
Technical Phone Screen
4
Onsite/Virtual Interviews
5
Final Decision
자주 나오는 질문
Technical Knowledge
Behavioral/STAR
Past Experience
Problem Solving
뉴스 & 버즈
Ninety One UK Ltd Cuts Position in Cadence Design Systems, Inc. $CDNS - MarketBeat
MarketBeat
News
·
3d ago
Moran Wealth Management LLC Sells 19,592 Shares of Cadence Design Systems, Inc. $CDNS - MarketBeat
MarketBeat
News
·
3d ago
Cadence Maps Its Future Beyond EDA With Agentic AI and Simulation - HPCwire
HPCwire
News
·
4d ago
Lesser-Known Cadence Design Systems Just Landed Google and Nvidia Deals. Should You Buy CDNS Stock? - Barchart.com
Barchart.com
News
·
4d ago



