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AMD
AMD

Together we advance.

RTL design Engineer with UPF ( Unified Power Format )

职能工程
级别中级
地点Hyderabad, India
方式现场办公
类型全职
发布3个月前

薪酬

CA$148,720 - CA$223,080

立即申请

福利待遇

医疗保险

育儿假

必备技能

C++

Python

Perl

Ruby

WHAT YOU DO AT AMD CHANGES EVERYTHING:

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.

Together, we advance your career.SENIOR SILICON DESIGN ENGINEERTHE ROLE: Join our leading-edge Design and RTL Methodology team as a Hardware Development Engineer, contributing directly to the development of our latest FPGA products. In this role, you will help ensure the highest quality of RTL design that our customers rely on.THE PERSON:
You are an experienced, proactive RTL Design Engineer who thrives in a fast-paced environment.  You quickly ramp up on new tools and methodologies, and you're comfortable working on a small, highly capable team where you can take on significant responsibility.

KEY RESPONSIBILITIES:

  • We will guide you as you ramp up on our RTL design and static verification tools and methodology ecosystem.

  • Collaborate with the design team to drive continuous improvements in front-end design methodologies, ensuring top-quality RTL across areas such as Lint, CDC, formal equivalence, and low-power verification.

  • Enhance and develop flows that analyze RTL and Unified Power Format (UPF) Files, including updating or creating new UPF to enable robust verification of power-domain crossings for AMD's next-generation monolithic and stacked FPGA-SoC product families.

  • Leverage corporate AI systems to increase productivity and streamline workflows.

PREFERRED EXPERIENCE:

  • Proven experience in logic design and static verification (System Verilog, Verilog, or VHDL), with contributions to one or more ASIC products brought to market.
  • Strong background in RTL/logic design, including specifying multi-power-domain architectures using IEEE 1801 Unified Power Format (UPF).
  • Programming skills in Perl, Python, and TCL

ACADEMIC CREDENTIALS:

  • Bachelor's degree in Electrical or Computer Engineering; Master's degree preferred.

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

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关于AMD

AMD

AMD

Public

Advanced Micro Devices, Inc. (AMD) is an American multinational semiconductor company headquartered in Santa Clara, California.

10,001+

员工数

Santa Clara

总部位置

$240B

企业估值

评价

10条评价

3.7

10条评价

工作生活平衡

2.8

薪酬

3.2

企业文化

4.1

职业发展

3.4

管理层

3.8

68%

推荐率

优点

Great team culture and spirit

Innovative projects and cutting-edge technology

Supportive management and leadership

缺点

High workload and overwhelming demands

Work-life balance challenges

High pressure and stressful deadlines

薪资范围

6个数据点

L2

L6

L3

L4

L5

L2 · Data Analyst L2

0份报告

$76,430

年薪总额

基本工资

$30,572

股票

$38,215

奖金

$7,643

$53,501

$99,359

面试评价

2条评价

难度

3.0

/ 5

时长

14-28周

录用率

50%

面试流程

1

Application Review

2

Recruiter Screen

3

Hiring Manager Interview

4

Technical Interview

5

Offer

常见问题

Technical Knowledge

Behavioral/STAR

Past Experience

Problem Solving