トレンド企業

AMD
AMD

Together we advance.

RTL design Engineer with UPF ( Unified Power Format )

職種エンジニアリング
経験ミドル級
勤務地Hyderabad, India
勤務オンサイト
雇用正社員
掲載3ヶ月前

報酬

CA$148,720 - CA$223,080

応募する

福利厚生

健康保険

育児休暇

必須スキル

C++

Python

Perl

Ruby

WHAT YOU DO AT AMD CHANGES EVERYTHING:

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.

Together, we advance your career.SENIOR SILICON DESIGN ENGINEERTHE ROLE: Join our leading-edge Design and RTL Methodology team as a Hardware Development Engineer, contributing directly to the development of our latest FPGA products. In this role, you will help ensure the highest quality of RTL design that our customers rely on.THE PERSON:
You are an experienced, proactive RTL Design Engineer who thrives in a fast-paced environment.  You quickly ramp up on new tools and methodologies, and you're comfortable working on a small, highly capable team where you can take on significant responsibility.

KEY RESPONSIBILITIES:

  • We will guide you as you ramp up on our RTL design and static verification tools and methodology ecosystem.

  • Collaborate with the design team to drive continuous improvements in front-end design methodologies, ensuring top-quality RTL across areas such as Lint, CDC, formal equivalence, and low-power verification.

  • Enhance and develop flows that analyze RTL and Unified Power Format (UPF) Files, including updating or creating new UPF to enable robust verification of power-domain crossings for AMD's next-generation monolithic and stacked FPGA-SoC product families.

  • Leverage corporate AI systems to increase productivity and streamline workflows.

PREFERRED EXPERIENCE:

  • Proven experience in logic design and static verification (System Verilog, Verilog, or VHDL), with contributions to one or more ASIC products brought to market.
  • Strong background in RTL/logic design, including specifying multi-power-domain architectures using IEEE 1801 Unified Power Format (UPF).
  • Programming skills in Perl, Python, and TCL

ACADEMIC CREDENTIALS:

  • Bachelor's degree in Electrical or Computer Engineering; Master's degree preferred.

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

閲覧数

0

応募クリック

0

Mock Apply

0

スクラップ

0

AMDについて

AMD

AMD

Public

Advanced Micro Devices, Inc. (AMD) is an American multinational semiconductor company headquartered in Santa Clara, California.

10,001+

従業員数

Santa Clara

本社所在地

$240B

企業価値

レビュー

10件のレビュー

3.7

10件のレビュー

ワークライフバランス

2.8

報酬

3.2

企業文化

4.1

キャリア

3.4

経営陣

3.8

68%

知人への推奨率

良い点

Great team culture and spirit

Innovative projects and cutting-edge technology

Supportive management and leadership

改善点

High workload and overwhelming demands

Work-life balance challenges

High pressure and stressful deadlines

給与レンジ

6件のデータ

L2

L6

L3

L4

L5

L2 · Data Analyst L2

0件のレポート

$76,430

年収総額

基本給

$30,572

ストック

$38,215

ボーナス

$7,643

$53,501

$99,359

面接レビュー

レビュー2件

難易度

3.0

/ 5

期間

14-28週間

内定率

50%

面接プロセス

1

Application Review

2

Recruiter Screen

3

Hiring Manager Interview

4

Technical Interview

5

Offer

よくある質問

Technical Knowledge

Behavioral/STAR

Past Experience

Problem Solving