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Snr. Product Development Engineer - Debug /Failure Analysis

AMD

Snr. Product Development Engineer - Debug /Failure Analysis

AMD

Singapore

·

On-site

·

Full-time

·

2mo ago

福利厚生

Learning

Healthcare

Flexible Hours

必須スキル

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Snr.

Product Development Engineer:

  • Debug /Failure Analysis

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  • Singapore, Singapore
  • Engineering
  • 75457

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Job Description

WHAT YOU DO AT AMD CHANGES EVERYTHING:

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

THE ROLE:

Returns Debug and RMA execution in Quality & Reliability organization, provide supportive functions to the organization to ensure customer quality issue being addressed evoking the required actions via failure analysis to improve product quality.

THE PERSON:

You will also need to possess strong verbal and written communication skills which are essential when working with a global team. A proactive, outstanding teammate who focuses on teamwork, team building, and growing team success.

AMD's environment is fast paced, results oriented and built upon a legion of forward-thinking people with a passion for winning technology!

KEY RESPONSIBILITIES:

  • Perform analysis & report writing on customer returns electrical FA, include analysis on Automated Test Equipment (ATE) and System Level Test (SLT), duplicate customer reported failure on Platform level and perform board level debug.
  • Customer returns debug covering pre & post Mass Production, field return including Excursion/Critical issue, also cover debug for Defect Part Per Million (DPPM) improvement.
  • Drive cross-functional collaboration by proactively engaging with Device Analysis and Product Engineering teams to lead fault isolation and root-cause investigations.
  • Identify and define test coverage enhancements that strengthen product quality, prevent customer-facing failures, and support long-term reliability improvements.
  • Provide technical direction in diagnosing complex issues, influencing validation strategies, and ensuring findings translate into actionable quality improvements across functions.
  • Provide conclusive and convincing results and align with Program/PLQ/Customer Interfacing team on final analysis report writing for customer communication.
  • Local product ownership roles that include but not limited to understanding, tracking and releases of ATE/SLT/OSV which covers RMA/OSV program, test program contents, and Go-To person on owned product technical queries.
  • Role model as a coach for internal team that able to guide junior on technical challenges that arise during work for specific IP or failure category.
  • Other duties as assigned by supervisor.

PREFERRED EXPERIENCE:

  • Strong in silicon debug or Failure Analysis knowledge either on electronics system level or Integrated Chip.
  • Candidate should be analytical and detail oriented, strongly interested in debugging complex system, self-starter, and fast learner
  • Experience working in root causes digital or analog failure or SCAN/MBIST/High Speed Loopback failure.
  • GPU, CPU or x86 architecture knowledge is much preferred
  • Java, Python, Perl coding or Linux Shell scripting skills
  • Window and Linux proficiency.
  • JTAG knowledge is a plus.
  • Knowledge in ATE test class/method experience with Advantest 93k platform is a plus.
  • Experience in computing hardware, PC systems or Server platform projects or task is a plus.
  • Knowledge or experience in PCB board or Customer Reference Board platform (schematics, layout, hardware configuration/setup, platform validation) is a plus
  • Knowledge in industry standards like PCIE, USB, or high bandwidth memory is a strong plus
  • Experience in AI or Machine Learning project or task is a plus.

ACADEMIC CREDENTIALS:

  • Bachelor’s or Master’s degree in Electrical/Electronic Engineering or Computer Engineering

LOCATION:

Singapore

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.
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模擬応募者数

0

スクラップ

0

AMDについて

AMD

AMD

Public

Advanced Micro Devices, Inc. (AMD) is an American multinational semiconductor company headquartered in Santa Clara, California.

10,001+

従業員数

Santa Clara

本社所在地

$240B

企業価値

レビュー

3.7

10件のレビュー

ワークライフバランス

2.8

報酬

3.2

企業文化

4.1

キャリア

3.4

経営陣

3.8

68%

友人に勧める

良い点

Great team culture and spirit

Innovative projects and cutting-edge technology

Supportive management and leadership

改善点

High workload and overwhelming work demands

Work-life balance challenges

High pressure and stressful deadlines

給与レンジ

6件のデータ

L2

L3

L4

L5

L6

M3

M4

M5

M6

L2 · Graphic Designer L2

0件のレポート

$162,512

年収総額

基本給

$65,005

ストック

$81,256

ボーナス

$16,251

$113,758

$211,266

面接体験

2件の面接

難易度

3.0

/ 5

期間

14-28週間

内定率

50%

面接プロセス

1

Application Review

2

Recruiter Screen

3

Hiring Manager Interview

4

Technical Interview

5

Offer

よくある質問

Technical Knowledge

Behavioral/STAR

Past Experience

Problem Solving