热门公司

招聘

职位AMD

Senior Verification Architect – Simulation & Methodology

AMD

Senior Verification Architect – Simulation & Methodology

AMD

Hyderabad

·

On-site

·

Full-time

·

2mo ago

福利待遇

Learning

Healthcare

必备技能

TypeScript

Node.js

JavaScript

Back

Senior Verification Architect – Simulation & Methodology

JOB_DESCRIPTION.SHARE.HTML
CAROUSEL_PARAGRAPH

  • JOB_DESCRIPTION.SHARE.HTML
  • Hyderabad, India
  • Engineering
  • 75356

mail_outline
Get future jobs matching this search
Loginor Register

Job Description

WHAT YOU DO AT AMD CHANGES EVERYTHING:

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

MTS SILICON DESIGN ENGINEER:

THE ROLE:

The AMD Verification Methodology and Technology (VMT) team delivers verification methodology and technology for all AMD teams and products. Team member will be working with global teams on the verification methodologies and technologies covering design technology, functional verification technology, coverage, debug and automation methodologies.

THE PERSON:

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES:

The successful candidate will assume technical responsibilities and hands-on technical architect role responsible for providing complex design methodologies in the hardware design verification space. The following is a list of key responsibilities that the candidate will assume:

  • Be a part of a wider team of technical experts in design verification and testbenches in AMD's Central R&D team
  • Be hands on technical contributor in the space of hardware description languages such as Verilog, testbench languages such as System Verilog
  • Play an expert role in verification methodologies and have extensive knowledge on UVM based testbenches
  • Possess and utilize in-depth knowledge in functional and code coverage technology and methodology to achieve faster coverage closure
  • Drive methodology around SOC/IP verification, VIPs, UVCs and BFMs
  • Demonstrate and utilize strong debugging skills in industry standard SOC/IP design & verification tools
  • Have knowledge of Verification Management tools and methodologies
  • Play a strong role in understanding AMD's existing systems, creating new ones, defining roadmaps on all verification methodologies, tools and flows
  • Knowledge of C/C++ based testbench architectures
  • Develop flows and methodology to integrate multiple independent testbenches/designs into a larger design and verification model
  • Simulation Performance analysis of existing designs, testbenches to keep up with the growing design sizes

PREFERRED EXPERIENCE:

  • 7+ years of experience

  • Proficient in IP level ASIC verification

  • Proficient in debugging firmware and RTL code using simulation tools

  • Proficient in using UVM testbenches and working in Linux and Windows environments

  • Experienced with Verilog, System Verilog, C, and C++

  • Graphics pipeline knowledge

  • Developing UVM based verification frameworks and testbenches, processes and flows

  • Automating workflows in a distributed compute environment.

  • Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process

  • Strong background in the C++ language, preferably on Linux with exposure to Windows platform

  • Good understanding and hands-on experience in the UVM concepts and System Verilog language

  • Good working knowledge of SystemC and TLM with some related experience.

  • Scripting language experience: Perl, Ruby, Makefile, shell preferred.

  • Exposure to leadership or mentorship is an asset

  • Desirable assets with prior exposure to video codec system or other multimedia solutions.

ACADEMIC CREDENTIALS:

  • Bachelors or Masters degree in computer engineering/Electrical Engineering

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.
Apply JOB_DESCRIPTION.SHARE.HTML
CAROUSEL_PARAGRAPH
JOB_DESCRIPTION.SHARE.HTML

总浏览量

0

申请点击数

0

模拟申请者数

0

收藏

0

关于AMD

AMD

AMD

Public

Advanced Micro Devices, Inc. (AMD) is an American multinational semiconductor company headquartered in Santa Clara, California.

10,001+

员工数

Santa Clara

总部位置

$240B

企业估值

评价

3.7

10条评价

工作生活平衡

2.8

薪酬

3.2

企业文化

4.1

职业发展

3.4

管理层

3.8

68%

推荐给朋友

优点

Great team culture and spirit

Innovative projects and cutting-edge technology

Supportive management and leadership

缺点

High workload and overwhelming work demands

Work-life balance challenges

High pressure and stressful deadlines

薪资范围

6个数据点

L2

L3

L4

L5

L6

L2 · Data Analyst L2

0份报告

$76,430

年薪总额

基本工资

$30,572

股票

$38,215

奖金

$7,643

$53,501

$99,359

面试经验

2次面试

难度

3.0

/ 5

时长

14-28周

录用率

50%

面试流程

1

Application Review

2

Recruiter Screen

3

Hiring Manager Interview

4

Technical Interview

5

Offer

常见问题

Technical Knowledge

Behavioral/STAR

Past Experience

Problem Solving