WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.  Together, we advance your career.

THE ROLE:

As a Timing Closure Engineer, you will join AMD’s IP team to develop high-performance Server IP for adaptive computing. You will collaborate closely with the Physical Design team, IP designers, and Top-level designers across multiple sites to ensure successful timing closure and contribute to building products that accelerate next-generation computing experiences.

KEY RESPONSIBILITIES:

• Work with Physical Design, IP, and Top-level design teams across multiple sites to achieve IP timing closure.
• Perform advanced timing analysis and develop STA constraints.
• Define clocks and ensure accurate STA implementation.
• Root cause timing issues in physical design or design architecture.
• Perform timing analysis and provide feedback or suggestions to RTL designers and Physical design engineers to resolve timing issues.
• Analyze Clock Tree Synthesis (CTS) performance and provide recommendations for optimization.
• Resolve complex issues in STA and RTL domains.
• Make technical decisions and provide design guidance.
• Mentor and coach junior engineers.

PREFERRED EXPERIENCE:

• Expert-level STA skills; proficient with DC and PT tools and commands.
• Hands-on experience in timing closure for high-frequency designs.
• Specialized knowledge of high-bandwidth internal data fabric is a plus.
• Strong Verilog RTL design experience for large-scale digital IP.
• Familiarity with logic/physical synthesis, DFT, and PHY integration.
• Familiar with multiple power domain designs, low-power design techniques, and UPF.
• Ability to work independently with strong task scheduling and milestone commitment.
• Fluent in English for communication, presentations, and documentation.
• Proven ability to solve complex, novel, and non-recurring problems.

EDUCATION & EXPERIENCE:

MS in Electrical Engineering or Computer Science with 7+ years of experience, or

BS in Electrical Engineering or Computer Science with 9+ years of experience.

LOCATION:

Hsinchu / Taipei

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.