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STAFF SILICON DESIGN ENGINEER:

THE ROLE:

This is an exciting opportunity to join the innovative and multi-award winning team that has developed the RF data converter sub-system, including direct-RF digital signal processing, around which Xilinx Zync® Ultrascale+™ RFSoC is built. As part of the Analog and Digital-RF design group you will be working on leading-edge digital communications developments in advanced mixed-signal environment using the latest 7nm and 16nm FinFET CMOS processes.

The role requires an experienced digital design engineer to work on all aspects of the front-end digital design flow including architecture specification and RTL design and optimisation, as well as some verification and synthesis.  This will involve extensive interactions with the analog design team, digital verification team, synthesis and place-and-route team.  The successful candidate will also be expected to perform a technical leadership role within the team and to promote best design practice within the team.

THE PERSON:

A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.

KEY RESPONSIBLITIES:

• Expert front-end design experience in a modern IC / ASIC design environment
• Experience in leading digital IC design teams
• Extensive experience of tools and design flows including RTL design and verification, CDC checking, linting, DFx, power estimation and design for low power
• Expert knowledge of System Verilog and logic design concepts
• Excellent written and oral communication skills
• Excellent problem solving skills
• Ability to work well as part of a collaborative multi-site interdisciplinary team
• Awareness of physical design flows including synthesis, STA, P&R
• Good awareness of physical implementation constraints on design and design optimization

PREFERRED EXPERIENCE:

• Experience in high speed wireless communications
• Strong knowledge of DSP fundamentals and extensive experience in implementing DSP in ASIC hardware
• Experience of Matlab / Octave algorithm development and architecture modelling
• Experience of power management techniques / UPF
• Experience of designing on the analog/digital boundary
• Knowledge of modern digital verification techniques such as UVM

ACADEMIC CREDENTIALS:

• Minimum education level / experience: BS + 8 years, MS + 7 years, PhD + 5 years

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Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.