RTL Engineer III, Silicon Cloud

RTL Engineer III, Silicon Cloud

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corporate_fareGoogleplaceBengaluru, Karnataka, India

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Mid

Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

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Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

• 4 years of experience in ASIC development with Verilog/System Verilog, Very High Speed Integrated Circuit (VHSIC), Hardware Description Language (VHDL), or Chisel.

• Experience with micro-architecture and designing IPs and subsystems.

• Experience in one coding/scripting language (e.g., Python, Perl).

Preferred qualifications:

• Master's or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science.

• Experience in System on a Chip (SoC) designs and integration flows.

• Experience in AI/ML.

• Knowledge of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies.

• Knowledge of high performance and low power design techniques.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will be part of a team developing Application-Specific Integrated Circuit (ASICs) used to accelerate machine learning computation in data centers. You will collaborate with members of architecture, verification, power and performance, and physical design to specify and deliver quality designs for next-generation data center accelerators. You will solve technical problems with micro-architecture and practical reasoning solutions, and evaluate design options with complexity, performance, power.

The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

Responsibilities

• Drive design methodology, libraries, debug, code review in co-ordination with other IP Design Verification (DV) teams and Physical Design teams.

• Identify and drive power, performance and area of improvements.

• Participate in design, implementation and integration of chassis and subsystems.

• Perform RTL coding for Subsystems/SoC integration, function/performance simulation debug, Lint/CDC/FV/UPF checks.

• Perform quality check flows like Lint, CDC, RDC, VCLP.

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Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire.

If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

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Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.