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DFT Engineer

職種エンジニアリング
経験ミドル級
勤務地USA-CA San Jose Innovation Drive
勤務オンサイト
雇用正社員
掲載1週間前
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Job Description:

Principal DFT Engineer:

Broadcom's ASIC Product Division is seeking candidates for a DFT position at our San Jose, California, Development Center. The successful candidate will be responsible for leading DFT programs all the way from chip level DFT specification, through to implementation and verification culminating in successfully releasing products to production.

The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Products Division)’s designs – DFT Architecture, Test insertion and verification, Pattern generation, Coverage improvement, Post silicon debug and yield improvement to meet the product test metrics. It involves working with the Physical Design & STA team for DFT mode timing closure. The role could also involve direct interaction with external customers.

It is expected that you can code using TCL, PERL, RUBY, PYTHON, C++ or similar.

Responsibilities:

  • Understanding Broadcom & customer DFT feature requirements & DPPM goals & defining appropriate DFT specifications for the ASIC

  • Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, Ser Des and other I/P DFT integration

  • Working closely with STA and DI Engineers design closure for test

  • Generating, Verifying & Debugging Test vectors before tape release.

  • Validating & Debugging Test vectors on ATE during the silicon bring up phase

  • Assisting with silicon failure analysis, diagnostics & yield improvement efforts

  • Interfacing with the customer, physical design and test engineering/manufacturing teams located globally

  • Working closely with I/P DFT engineers & other stakeholders

  • Debugging customer returned parts on the ATE

  • Innovating newer DFT solutions to solve testability problems in 7nm & beyond

  • Automating DFT & Test Vector Generation flows

Skills/Experience:

  • Strong DFT background (such as IO and Analog DFT, ATPG and/or Scan, BIST, and others)

  • Scan Insertion and scan compression background (DFT Compiler, Mentor Test Kompress, etc.)

  • Well-versed in ATPG vector generation, simulation, and debugging. (Tetra Max, Fastscan)

  • Experience in Verilog coding, testbench generation & simulation

  • Memory BIST insertion and verification experience on embedded (SRAM, CAM, eDRAM, ROM)

  • Boundary scan Verification and test vector generation. Should have good knowledge in IEEE1149.1 and IEEE1149.6

  • Basic knowledge Test-STA and constraints

  • Strong background on IEE1687, IJTAG, ICL and PDL

  • The ability to work in a multi-disciplined, cross-department environment

  • Solid knowledge in analog and digital circuit design, and device physics fundamentals

  • Good understanding of Si processing, logical and physical synthesis, and transistor reliability principles

  • Excellent problem solving, debug , root cause analysis and communication skills

  • Experience working on the ATE is a plus

  • Experience with Serdes, DDR, PCIE, ENET, CXL IOBIST verification and silicon debug is a plus

  • Experience working on Tessent SSN is a plus

Education & Experience:

  • Bachelors in Electrical/Electronic/Computer Engineering and 12+ years of relevant industry experience or Masters Degree in Electrical/Electronic/Computer Engineering and 10+ years of relevant industry experience

Additional Job Description: Compensation and Benefits

The annual base salary range for this position is $141,300 - $226,000

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

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VMwareについて

VMware

VMware

Acquired

Realize what's possible.

10,001+

従業員数

Palo Alto

本社所在地

レビュー

10件のレビュー

3.7

10件のレビュー

ワークライフバランス

4.0

報酬

3.8

企業文化

2.5

キャリア

2.8

経営陣

2.2

35%

知人への推奨率

良い点

Good benefits and perks

Great company culture (pre-acquisition)

Work-life balance

改善点

Broadcom acquisition ruined company culture

Poor leadership and management decisions

Limited career growth and learning opportunities

給与レンジ

5件のデータ

Mid/L4

Mid/L4 · Client Services Consultant

1件のレポート

$172,424

年収総額

基本給

$149,760

ストック

-

ボーナス

-

$172,424

$172,424

面接レビュー

レビュー10件

難易度

3.0

/ 5

期間

14-28週間

内定率

70%

体験

ポジティブ 30%

普通 50%

ネガティブ 20%

面接プロセス

1

Application Review

2

HR/Recruiter Screen

3

Technical Phone Screen

4

Onsite/Virtual Interviews

5

Reference Check

6

Offer

よくある質問

Coding/Algorithm

Technical Knowledge

Behavioral/STAR

System Design

Past Experience