Internship, SI Hardware RTL Design Engineer, SI Hardware (Winter/Spring 2027)

What to Expect

Consider before submitting an application:

This position is expected to start January 2027 and continue through Spring term (ending approximately April 2026). We ask for a minimum of 12 weeks, full-time (40 hours/week) and on-site, for most internships. Our internship program is for students who are actively enrolled in an academic program. Recent graduates seeking employment after graduation and not returning to school should apply for full-time positions, not internships.

International Students: If your work authorization is through CPT, please consult your school on your ability to work 40 hours per week before applying. You must be able to work 40 hours per week on-site. Many students will be limited to part-time during the academic year.

The Internship Recruiting Team is driven by the passion to recognize and develop emerging talent. Our year-round program places the best students in positions where they will grow technically, professionally, and personally through their experience working closely with their Manager, Mentor, and team. We are dedicated to providing an experience that allows the intern to experience life at Tesla by including them in projects that are critical to their team’s success.

Multiple Locations Possible: Palo Alto, CA; Austin, TX

What You’ll Do

• Micro-architecture specification and design
• Deliver Performance, Area and Power-efficient RTL design
• Specification, microarchitecture, and RTL design of accelerators, memory and network subsystems
• Work with the architecture and software teams to achieve design targets
• Balance performance, power, safety, and cost requirements
• Trade-off functional, physical and performance requirements
• Work with cross-functional teams, including implementation, verification, and performance engineers
• Design for synthesis

What You’ll Bring

• Currently pursuing a degree in Computer Engineering, Electrical Engineering, or a related field with a graduation date between May 2027 - December 2027
• High performance (low latency, high bandwidth) design techniques
• Area and power-efficient complex RTL design
• Low power microarchitecture techniques
• Verilog RTL logic design
• Experience with simulators and waveform debug tools
• Knowledge of logic design principles, including timing and power implications
• Experience with IEEE floating point is a plus
• Experience with high speed SERDES or SOC design is a plus