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职位Silicon Labs

Senior Engineer - Analog/Mixed signal/RFIC circuit design in CMOS (3 to 6years)

Silicon Labs

Senior Engineer - Analog/Mixed signal/RFIC circuit design in CMOS (3 to 6years)

Silicon Labs

Hyderabad

·

On-site

·

Full-time

·

1mo ago

福利待遇

Equity

Flexible Hours

Parental Leave

必备技能

Analog circuit design

Mixed-signal design

RFIC design

CMOS design

Schematic design

Transistor-level simulation

Low-power design

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated So Cs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com.

Why Silicon Labs:

Innovation doesn't start with companies; it starts with people. We put people first in everything we do, whether it’s employees we work with every day, our customers developing new devices, or the people in communities where we operate. Our incredibly talented team is comprised of innovative risk-takers pushing the bounds of what’s possible. We're problem solvers first, addressing industry’s biggest challenges to transform industries, grow economies and improve lives.

Meet The Team:

We are the Hyderabad RF IC design team responsible for the Wi-Fi and Bluetooth radio designs, working closely with the Modem design, Analog/RF IC layout , RF Validation , CAD, PTE, Packaging, Module design, HW tools, Apps and SW teams among other teams. We are a mix of junior and experienced engineers with the current head count of ~15 members. We take pride in getting the chip to perform as designed in the very first tape out. RF design is at the core of the wireless performance that our state of the art chips exhibit. Most of the wireless datasheet parameters are a directly related to how the radio performs. We focus on optimizing the power, performance and die area ( aka PPA

The Role:

You’ll contribute to the design and development of state-of-the-art Wi-Fi/Bluetooth products, focusing on low-power, high-performance RF and analog circuits. You’ll work closely with senior engineers, learning the full design flow from concept to silicon validation.

Responsibilities:

· Contribute to the design, simulation, and verification of analog/RF building blocks (LNAs, mixers, baseband filters, dividers, PAs, etc.) in advanced CMOS technologies.

· Support integration and characterization of analog/RF sub-systems such as Rx, Tx, and synthesizer blocks.

· Perform schematic design, transistor-level simulation, and assist in layout verification and reviews.

· Participate in silicon validation and debug, correlating lab measurements with simulations.

· Work with cross-functional teams (system, digital, layout, and test engineering) to ensure successful product integration.

· Support documentation and review processes for design blocks.

· Apply low-power design principles and techniques to meet aggressive power and performance targets.

Preferred Skills:

· Experience in Analog/Mixed signal/RFIC circuit design in CMOS

· Prior experience in designing one or more of the following RF circuits in CMOS (0.13u or lower geometries): LNAs, Mixers(active/Passive), Baseband Filters, I/Q data converters, High frequency LO Dividers, High power CMOS Pas

· Experience with EM modeling tools and passive components (inductors, transformers) is a plus.

· Basic scripting knowledge in Python, SKILL, Shell, etc. for design automation is desirable.

· Good understanding of RF system fundamentals, modulation/demodulation, and wireless transceiver architectures.

· Good understanding of device noise, mismatch, linearity, and other RF and analog impairments

· Strong knowledge of RF design and implementation techniques

· Proficiency in Cadence Design Environment for Analog, Mixed-Signal and RF designs (Cadence Analog Artist, Cadence Virtuoso, SpectreRF, EMX, AFS etc.)

· Ability to drive strong production test/QA methodologies

· Excellent written and verbal presentation skills required.

Experience with artificial intelligence (AI) powered tools and technologies used to enhance productivity, analysis, and decision-making"

Minimum Qualifications:

Senior Engineer: 3–6 years of relevant industry experience.

BS/MS/MSc/Ph. D in Electronics/ Electrical/ Integrated Circuits Engineering

Benefits & Perks:

Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun.

  • Equity Rewards (RSUs)
  • Employee Stock Purchase Plan (ESPP)
  • Insurance plans with Outpatient cover
  • National Pension Scheme (NPS)
  • Flexible work policy
  • Childcare support

Silicon Labs is an equal opportunity employer and values the diversity of our employees. Employment decisions are made on the basis of qualifications and job-related criteria without regard to race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status, or any other characteristic protected by applicable law.

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关于Silicon Labs

Silicon Labs

Silicon Laboratories, Inc., commonly referred to as Silicon Labs, is a fabless global technology company that designs and manufactures semiconductors, other silicon devices and software, which it sells to electronics design engineers and manufacturers in Internet of Things (IoT) infrastructure...

1,001-5,000

员工数

Austin

总部位置

$5.2B

企业估值

评价

3.5

1条评价

工作生活平衡

3.0

薪酬

3.0

企业文化

3.5

职业发展

3.5

管理层

3.0

75%

推荐给朋友

优点

Fast-moving hiring process

No online assessment required

Casual technical interview approach

缺点

Nerve-wracking interview environment

Senior engineer observation creates pressure

Intense coding problems

薪资范围

1个数据点

Intern

Intern · Embedded SWE Intern

1份报告

-

年薪总额

基本工资

-

股票

-

奖金

-

面试经验

1次面试

难度

2.0

/ 5

时长

14-28周

录用率

100%

体验

正面 100%

中性 0%

负面 0%

面试流程

1

Application Review

2

Resume Screen

3

First Technical Interview

4

Second Technical Interview

5

Phone Offer

6

Official Offer

常见问题

Coding/Algorithm

Technical Knowledge

Embedded Systems

Behavioral/STAR