招聘
Location: Stansted, UK
Our Team:Semtech’s High-Speed IC Design team is a globally distributed group of expert engineers focused on developing cutting-edge analog and mixed-signal semiconductor solutions.
Working across our Stansted and Ottawa design centres, the team specialises in transimpedance amplifiers (TIAs) and laser drivers (LDs) that enable high-speed data communication for datacentres, 5G networks, and fibre-to-the-home infrastructure.
With a strong track record of innovation and global collaboration, the team plays a critical role in delivering industry-leading IC products.
Job Summary:The Principal Analog Design Engineer is responsible for leading the design and development of high-speed analog ICs from concept through to volume production.
This role serves as a key technical authority within the team, driving innovation in circuit architecture, leading chip development projects, and ensuring high-performance, manufacturable designs that meet product and customer requirements.
Responsibilities:
- Lead the design and development of high-speed analog ICs, delivering robust, high-quality designs that meet defined specifications and timelines (40%).
- Take ownership of critical chip subsystems and act as technical lead across cross-functional project teams (20%).
- Collaborate closely with Marketing, Product Definition, Test, Verification, Reliability, and Product Engineering teams to ensure successful product development (15%).
- Drive innovation in circuit design and architecture, introducing new ideas and solutions to improve performance and efficiency (10%).
- Mentor and support junior engineers, providing technical guidance and fostering team development (10%).
- Communicate complex technical concepts clearly through reports and presentations to senior stakeholders (5%).
Minimum Qualifications:
- Bachelor’s degree in Electrical, Electronics, or related Engineering field.
- 15+ years’ experience in analog IC design within the semiconductor industry.
- Deep understanding of CMOS/BiCMOS analog circuit design practices.
- Proven experience as a technical lead on chip development projects.
- Strong RF analog design experience (10 GHz+).
- Expert proficiency with Cadence design and simulation tools.
- Solid understanding of RF/analog layout techniques, including parasitics, matching, ESD, crosstalk, and IR drop.
- Demonstrated innovation and creative problem-solving capabilities.
- Fluent in written and spoken English.
Desired Qualifications:
- Postgraduate qualification (MSc or equivalent) in a relevant field.
- Experience with circuit design at 25 GHz and above.
- Prior experience designing laser drivers and/or transimpedance amplifiers (TIAs).
- Knowledge of high-frequency component design, including T-coils, inductors, and 3D modelling.
- Experience with high-frequency lab validation techniques and equipment.
- Understanding of design for manufacturability (DFM), reliability, and yield optimisation.
- Experience with device modelling (Verilog-AMS, System Verilog).
- Familiarity with optoelectronic components such as PIN diodes, lasers, and Mach-Zehnder modulators (MZMs).
Career Growth Philosophy:At Semtech, we believe that innovation starts with people. We are committed to empowering professional development through mentorship, continuous learning resources, and a collaborative, idea-rich engineering environment.
Our pay-for-performance culture rewards initiative, encourages growth, and recognises meaningful technical and leadership contributions. Engineers in this role are supported to expand their influence, deepen their expertise, and shape both their career progression and the future of Semtech’s digital engineering capabilities.
Additional Notes:
The intent of this job description is to describe the major duties and responsibilities performed by incumbents of this job. Incumbents may be required to perform job-related tasks other than those specifically included in this description.
All duties and responsibilities are essential job functions and requirements.
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关于Semtech

Semtech
PublicSemtech Corp supplies analog, mixed-signal semiconductors, and algorithms for enterprise, communication, and industrial applications.
1,001-5,000
员工数
Camarillo
总部位置
$1.2B
企业估值
评价
2.9
10条评价
工作生活平衡
3.8
薪酬
2.5
企业文化
2.8
职业发展
3.2
管理层
1.8
25%
推荐给朋友
优点
Great people and coworkers
Good work-life balance and remote work options
Learning opportunities and career growth potential
缺点
Poor management and leadership
Political workplace culture
Below average compensation and benefits
薪资范围
41个数据点
Mid/L4
Principal/L7
Senior/L5
Mid/L4 · SAP APO Business Analyst
2份报告
$92,738
年薪总额
基本工资
$80,642
股票
-
奖金
-
$90,850
$94,628
面试经验
1次面试
难度
2.0
/ 5
时长
14-28周
面试流程
1
Application Review
2
HR Screen
3
Hiring Manager Interview
4
Skills Assessment
5
Offer
常见问题
Past Experience
Technical Knowledge
Attention to Detail
Data Management Skills
Culture Fit
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