채용
Location: Alhambra, CA (Onsite)
Position Summary: The Process Development Engineer – InP Wafer Fab position is responsible for development, optimization, and manufacturing support of deposition and etch process modules used in the fabrication of Indium Phosphide (InP)–based photonic devices, including DFB lasers, Semiconductor Optical Amplifiers (SOAs), and Gain Chip (GC) products. This role provides technical ownership of PECVD deposition processes and dry/wet etch technologies, serving as the primary process expert for dielectric films and plasma etch systems within the wafer fabrication facility. The position focuses on profile control, uniformity, yield improvement, manufacturing stability, and tool performance to enable robust and scalable production.
Responsibilities:
Deposition and Etch Process Development & Ownership (35%):
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Develop, qualify, and maintain PECVD dielectric deposition processes for InP-based device structures
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Develop and optimize dry etch (ICP-RIE/RIE) and wet etch processes for InP and related material systems
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Own PECVD and ICP-RIE/RIE tools, including recipe control, chamber conditioning, and process stability
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Define and maintain process windows, control limits, and equipment qualification requirements
Tool Ownership, Control, and Manufacturing Stability (25%) :
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Coordinate preventive maintenance and tool performance monitoring
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Drive process uniformity, film thickness control, etch profile control, and critical dimension (CD) performance
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Monitor tool health and respond to excursions impacting yield or reliability
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Support capacity scaling, equipment qualifications, and tool transfers
Failure Analysis and Root-Cause Resolution (20%):
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Lead and coordinate failure analysis (FA) activities using structured problem-solving methodologies (e.g., 8D, Six Sigma)
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Identify defect mechanisms and process-induced failure modes through cross-functional investigation
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Leverage FA techniques such as optical inspection, SEM, FIB, SIMS, and electrical analysis (directly or via partners)
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Ensure corrective and preventive actions are implemented and verified for effectiveness
Yield Improvement, Excursion Response, and Root-Cause Analysis (20%):
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Lead defect reduction and yield improvement initiatives related to deposition and etch processes
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Perform structured root-cause investigations using data analysis, DOE, and failure analysis inputs
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Analyze inline and electrical test data to identify trends, drifts, and emerging risks
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Implement corrective and preventive actions and verify long-term effectiveness
New Product Introduction and Technology Support (10%):
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Support new product introduction (NPI), process transfers, and technology scaling efforts
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Evaluate process risks associated with new materials, designs, and device structures
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Interface with photo, metallization, device, and manufacturing teams to resolve integration issues
Documentation, Process Control, and Manufacturing Support (10%)
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Author and maintain SOPs, process specifications, travelers, and control plans
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Define and maintain SPC metrics and control strategies for deposition and etch processes
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Provide hands-on manufacturing and on-call support as required
Minimum Qualifications:
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Bachelor’s degree or higher in Chemical Engineering, Materials Science, Electrical Engineering, Physics, or a related field
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Minimum of 3+ years of experience in semiconductor deposition and/or etch process engineering
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Hands-on experience with PECVD systems and ICP-RIE/RIE etch tools
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Strong hands-on understanding of InP-based or III-V compound semiconductor wafer fabrication processes
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Strong understanding of plasma processes, etch chemistries, and thin-film properties
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Demonstrated experience with profile control, uniformity improvement, and SPC
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Strong data analysis and problem-solving skills
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Ability to drive technical ownership in a manufacturing environment
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Preferred experience with InP or III-V compound semiconductor devices
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Familiarity with DFB lasers, SOAs, gain chips, or photonic device manufacturing preferred
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Experience supporting high-mix, low-volume manufacturing environments preferred
The intent of this job description is to describe the major duties and responsibilities performed by incumbents of this job. Incumbents may be required to perform job-related tasks other than those specifically included in this description.
All duties and responsibilities are essential job functions and requirements and are subject to possible modification to reasonably accommodate individuals with disabilities.
A reasonable estimate of the pay range for this position is $73,000 - $110,000. There are several factors taken into consideration in determining base salary, including but not limited to: job-related qualifications, skills, education and experience, as well as job location and the value of other elements of an employee’s total compensation package.
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Semtech 소개

Semtech
PublicSemtech Corp supplies analog, mixed-signal semiconductors, and algorithms for enterprise, communication, and industrial applications.
1,001-5,000
직원 수
Camarillo
본사 위치
$1.2B
기업 가치
리뷰
2.9
10개 리뷰
워라밸
3.8
보상
2.5
문화
2.8
커리어
3.2
경영진
1.8
25%
친구에게 추천
장점
Great people and coworkers
Good work-life balance and remote work options
Learning opportunities and career growth potential
단점
Poor management and leadership
Political workplace culture
Below average compensation and benefits
연봉 정보
41개 데이터
Mid/L4
Senior/L5
Mid/L4 · Product Engineering Manager
3개 리포트
$124,200
총 연봉
기본급
$108,000
주식
-
보너스
-
$124,200
$135,700
면접 경험
1개 면접
난이도
2.0
/ 5
소요 기간
14-28주
면접 과정
1
Application Review
2
HR Screen
3
Hiring Manager Interview
4
Skills Assessment
5
Offer
자주 나오는 질문
Past Experience
Technical Knowledge
Attention to Detail
Data Management Skills
Culture Fit
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