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Position Summary

Job Description Summary:

In your role as a Defect Reduction Engineer you'll support defect control and reduction work in a high volume 24x7 manufacturing environment, on purpose to achieve yield and performance goals.

Role and Responsibilities:

Here’s What You’ll Be Responsible For:

• Supports defect control and reduction work in a high volume 24x7 manufacturing environment, on purpose to achieve yield and performance goals.

• Supports New Product Introduction (NPI) as the Defect Reduction representative: attending meetings, presenting inline inspection strategy & methodology, supporting GPM set up, spec audits, and comparison, evaluating unit part process changes and tool spreads in terms of inline and NPW defectivity data.

• Performs fab process/tool trend data and correlation analysis to identify dog tools, trace defects to root cause, and rapidly take action to prevent inline process excursions.

• Works cross-functionally with YE/PIE/UP to evaluate defect data on BKMs & projects, excursion monitoring & control, SWLY reduction.

• Establishes FCC (Failed Chip Count) and trend monitoring plans for new technology introductions and ramps (14nm & foundry) and existing legacy production nodes (45nm/32nm/28nm) in order to achieve yield and performance goals, and support on weekly module meetings & activities. Respond to foundry customer requests and delivering the data & analysis to meet expectation.

• Supports new technology and process transfer projects from Samsung HQ (South Korea).

Skills and Qualifications

Here's what you'll need:

• Requires a Bachelor's degree in Electrical, Chemical, Mechanical Engineering, Material Science, Chemistry, Physics or related technical fields.

• 5+ years of Semiconductor process engineering experience in defect monitor and reduction.

• Experience in leading logic technology (45nm or below) development is strongly preferred.

• Relevant experience in advanced defect inspection and review tools (bright field, dark field, e-beam, Vis-edge…etc) is strongly preferred.

• Knowledge of Klarity Defect (or similar) software and its application in a semiconductor processing environment is useful.

• Working knowledge in SPC and DOE methodology is required

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The current base salary range for this role is between $70,480 - $179,090. Individual base pay rates will depend on factors including duties, work location, education, skills, qualifications and experience. Total compensation for this position will include a competitive benefits package and may include participation in company incentive compensation programs, which are based on factors to include organizational and individual performance.

Total Rewards At Samsung SAS, base pay is just one part of our total compensation package. The base compensation for this role will depend on education, experience, skills, and location.

We offer a comprehensive benefits package, including:

• Medical, dental, and vision insurance
• Life insurance and 401(k) matching with immediate vesting
• Onsite café(s) and workout facilities
• Paid maternity and paternity leave
• Paid time off (PTO) + 2 personal holidays and 10 regular holidays
• Wellness incentives and MORE

Eligible full-time employees (salaried or hourly) may also receive MBO bonuses based on company, division, and individual performance.

All positions at SAS are full-time on-site.

U.S. Export Control Compliance This role requires access to information subject to U.S. export control laws. Applicants must be authorized to access such information or eligible for government authorization.

Trade Secrets Notice:

By submitting an application, you agree not to disclose to Samsung—or encourage Samsung to use—any confidential or proprietary information (including trade secrets) belonging to a current or former employer or other entity.

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