Company:

Qualcomm Semiconductor Limited:

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

As a forward-thinking technology company, Qualcomm advances the limits of innovation in Industrial and Embedded IoT to deliver next generation experiences and accelerate digital transformation toward a smarter, more seamlessly connected world.We are seeking a seasoned Video Codec Design Engineer to join our SoC design team. In this role, you will architect and develop advanced video encoder and decoder hardware for high performance, low power semiconductor products. You will be responsible for defining micro architecture, modeling, implementing, optimizing, and validating video codec IP that meets stringent performance, area, and power targets. You will work closely with architecture, RTL, firmware, algorithm, physical design, and verification teams to deliver world class video solutions across a wide range of markets including IoT, mobile, automotive, and embedded systems.
This role requires both strong technical depth and cross functional collaboration to turn complex video standard requirements into efficient, production ready hardware designs.

Responsibilities:

• Architect, design, and optimize hardware blocks for video encoding and decoding, including motion estimation, motion compensation, transform/quantization, entropy coding, in loop filters, and rate control related datapaths.
• Translate video standard requirements (H.264/AVC, H.265/HEVC, AV1, VVC, etc.) into efficient micro architectures and hardware algorithms, ensuring scalability, configurability, and compliance.
• Build C/C++/SystemC models for performance, accuracy, and power estimation; perform algorithm to hardware decomposition to guide RTL implementation. (Consistent with modeling and algorithm decomposition responsibilities in internal files.) Video HWSYS Engineer | Word
• Partner with the systems and architecture teams to evaluate codec performance and analyze key KPIs such as throughput, latency, memory bandwidth, and quality metrics.
• Collaborate with verification teams to define test plans, functional coverage, and debug infrastructure for robust pre silicon validation.
• Drive integration of codec IP into SoC subsystems, ensuring seamless interaction with memory subsystems, firmware interfaces, and NoC/fabric components.
• Work with physical design teams to meet PPA targets through timing aware micro architecture, pipeline optimization, and clock/power domain planning.
• Support post silicon bring up and validation, analyze real chip performance, and propose architectural or firmware updates when needed.

Minimum Qualifications:

• Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• Strong understanding of video compression algorithms, transform coding, motion estimation/compensation, loop filters, and entropy coding.
• Experience in RTL design (Verilog/System Verilog), micro architecture, pipeline design, and hardware performance optimization.
• Proficiency in C/C++/Python/SystemC for modeling and architectural exploration.
• Solid grasp of SoC design concepts, including memory hierarchy, interconnect, bandwidth constraints, and power performance trade offs.
• Experience collaborating with verification, physical design, and firmware/software teams.

Preferred Qualifications:

• Experience contributing to or implementing modern video coding standards (HEVC, VVC, AV1, VP9).
• Nice to have experiences in scripting language.
• Nice to have experiences in FPGA flow

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. OR
  Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
  OR
  PhD in Science, Engineering, or related field.

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