Company:

Qualcomm Semiconductor Limited:

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

As a forward-thinking technology company, Qualcomm advances the limits of innovation in "Industrial and Embedded IoT" to deliver next-generation experiences and accelerate digital transformation toward a smarter, more seamlessly connected world.We are seeking a seasoned RTL Design Engineer to join our SoC design team. In this role, you will be responsible for architecting and implementing RTL designs for complex SoC platforms, with a focus on MIPI interface design and integration, covering both in-house controllers and 3rd party IPs. You will collaborate closely with verification, physical design, and system architecture teams to ensure seamless integration, robust functionality, and optimal performance.

Responsibilities:

• Define and implement RTL architecture for SoC subsystems
• Design, integrate, and evaluate MIPI controllers (in-house and 3rd party IPs)
• Develop and optimize RTL code for performance, power, and area efficiency
• Collaborate with verification teams to ensure functional correctness and coverage
• Work with physical design teams to achieve timing closure and DFT compliance
• Debug and resolve RTL issues across simulation, emulation, and silicon validation
• Drive methodology improvements and automation for RTL design flow
• Provide guidance on coding styles, interface protocols, and best practices
• Occasional business travel across APAC and other regions may be required

Minimum Qualifications

• Master’s degree in Electrical Engineering, Computer Engineering, or related field
• 7+ years of hands-on experience in RTL design and SoC integration
• Proficiency in Verilog/System Verilog and RTL design methodologies
• Solid experience with MIPI protocol, including both in-house controller design and 3rd party IP integration
• Familiarity with RTL-to-GDSII flow and timing closure
• Strong scripting skills in Python, Tcl, or Shell
• Excellent problem-solving and cross-functional communication skills

Preferred Qualifications

• Experience with low-power design techniques and clock/power domain crossing
• Knowledge of AMBA protocols (AXI, AHB, APB) and interconnect design
• Familiarity with post-silicon validation and debug of MIPI or other interface IPs
• Exposure to EDA tools such as Synopsys Design Compiler, VCS, or Cadence tools
• Comfortable working in a globally distributed engineering environment
• Experience correlating pre-silicon verification with post-silicon performance/yield

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. OR
  Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
  OR
  PhD in Science, Engineering, or related field.

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