Company:

Qualcomm Semiconductor Limited:

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

As a system architecture technologist on STCO, this role focuses on system level architecture definition and technology pathfinding for advanced So Cs and chiplet based platforms. The position drives early architecture, packaging, and technology trade off decisions for next generation products, with emphasis on AI driven workloads, system efficiency, and scalability. The role works closely with system architecture, packaging, and technology teams to translate requirements into quantitative system KPIs and figures of merit, enabling consistent system level evaluation across product generations.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. OR
  Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
  OR
  PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

This role focuses on system‑level STCO architecture definition and pathfinding for advanced So Cs leveraging 2.5D/3D and chiplet‑based architectures. The engineer defines system KPIs beyond PPAC, evaluates architecture–technology–packaging trade‑offs, and supports early, high‑impact design decisions for future platforms.

A key responsibility is to translate system and workload requirements into quantitative figures of merit (FOMs), including performance, power, thermal, yield, and AI efficiency and cost metrics, to support structured system‑level KPI evaluation and STCO decision platforms.

Minimum Qualifications:

• Experience with 2.5D and 3D STCO architecture and pathfinding, including chiplet‑based SoC systems.
• Strong understanding of system‑level KPIs, including bandwidth, latency, performance‑per‑watt, thermal behavior, power integrity, yield, and cost, and how these depend on architecture, process technology, and packaging.
• Solid knowledge of heterogeneous SoC and chiplet architectures, including partitioning across compute, accelerators, memory, and I/O, with understanding of trade‑offs impacting inter‑die communication, memory hierarchy, power delivery, thermal coupling, manufacturability, and system cost.
• Experience with workload‑driven system design, particularly for AI inference, AI acceleration, HPC, or high‑performance compute use cases.
• Understanding of AI system efficiency metrics, including tokens per second, tokens per watt, and cost per token, and how these metrics are influenced by architecture, memory bandwidth, interconnect, power, and thermal constraints.
• Ability to evaluate how system architecture and packaging decisions impact AI inference cost per token and overall system efficiency.
• Solid understanding of 2.5D/3D integration schemes, such as interposer‑based designs and stacked die concepts, and their implications on system planning.
• Awareness of advanced packaging constraints, including thermal management, power delivery, and mechanical considerations in multi‑die systems.
• Basic programming proficiency (e.g., Python or equivalent) to support system modeling or architectural trade‑off analysis.

Additional Qualifications:

• Demonstrated ability to work effectively across engineering and technology teams
• Ability to operate independently in early‑stage and ambiguous problem spaces
• Strong analytical skills for data‑driven architecture evaluation and interpretation

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