Company:

Qualcomm Semiconductor Limited:

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

Location: Hsinchu, Taiwan (Onsite, 5 days/week)

Must have keywords: 3DIC, DRAM Diagnostics, Bitmapping

Nice to have keywords: Yield, ATPG, AI

General Summary:

We are seeking an experienced engineer to lead the research, design, and development of advanced diagnostics solutions for 2.5D and 3DIC products with a strong focus on DRAM and wafer stacking interfaces. This role focuses on creating robust test and diagnostic methodologies across JTAG, scan (ATPG), memory (DRAM and SRAM), TSV and interposer structures, and system-level packaging interactions. The primary responsibility is to architect diagnostic flows, define test content, improve fault localization, and strengthen repair strategies that enhance overall product yield.

Key Responsibilities:

Diagnostics Architecture

• Architect end‑to‑end diagnostics solutions for 3DIC products, spanning wafer test, package-level test, and system-level test.
• Lead memory diagnostics architecture across SRAM, embedded DRAM, stacked DRAM, and emerging memory technologies.
• Specify and evolve BIST, BIRA/BISR, redundancy, and repair architecture to support efficient defect screening and yield recovery.
• Architect TSV and interposer diagnostic flows that emphasize failure signature capture, layer-to-layer isolation, suspect clustering, redundancy utilization, and stress-aware diagnostics.
• Collaborate with design teams to ensure diagnosability is designed in early, with clear test hooks, observability, and repair options.

Test Content & Methodology Development

• Define memory test algorithms, bitmap extraction flows, and signature formats to support accurate fault-mode classification and repair.
• Drive creation of test content that enables rapid isolation of inter-layer defects, packaging-induced failures, and thermal/mechanical stress effects.

Tool & Workflow Definition

• Guide enhancements to internal and EDA vendor diagnostic tools to support 3DIC‑specific failure modes.
• Define workflows for integrating memory, TSV, and diagnostics results with debug teams, FA labs, and yield engineering.

Cross-Functional Technical Leadership

• Partner closely with DFT, design, test, packaging, and manufacturing teams to ensure diagnostic requirements are understood and adopted.
• Lead technical deep dives on failure modes, test structures, and diagnosability limitations.
• Mentor junior engineers and guide the technical direction of diagnostic strategy for next‑generation 3DIC programs.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience. OR
  Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
  OR
  PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

Preferred Qualifications:

• Master’s or Ph.D. in Electrical Engineering, Computer Engineering, or related field.
• Extensive experience in diagnostics, DFT, test methodology, and silicon bring-up.
• Deep knowledge of memory DFT, BIST, redundancy/repair, and structural test content.
• Strong understanding of 2.5D/3DIC packaging, TSV/HBM structures, and related failure mechanisms.
• Proficiency with DFT/diagnostic tools from major EDA vendors.
• Clear, concise communication skills and demonstrated leadership in complex technical domains.

Preferred Skills:

• Experience designing or improving BIST/BIRA/BISR flows in advanced So Cs or 3DIC architectures.
• Background in memory diagnostics across SRAM, embedded DRAM, and stacked DRAM.
• Familiarity with packaging-induced defect mechanisms and associated test strategies.
• Experience influencing architecture decisions across multiple cross-functional teams.
• Ability to incorporate automation or AI-assisted methods selectively to improve diagnostic workflows.

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