채용

Physical Design Engineer - Multiple Levels
San Diego, California, United States of America; Santa Clara, California, United States of America; Austin, Texas, United States of America
·
On-site
·
Full-time
·
9mo ago
필수 스킬
Python
Linux
Company:
Qualcomm Technologies, Inc.
Job Area:
Engineering Group, Engineering Group > ASICS Engineering
General Summary:
As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.
QCTs Digital ASIC Team is actively seeking candidates for several physical design engineering positions in our SOC and core design team. As a physical design engineer you will innovate, develop, and implement chips and cores using state-of-the-art tools and technologies.
You will be part of a team responsible for the complete Physical Design Flow and deliveries of complex, high-speed, low power designs such as GPU, Camera and other MM, DDR, Modem, Audio . Tasks also involve the development and enablement of low power implementation methods, customized P&R to achieve area reduction, performance, and power goals. Additional responsibilities in this role involves good understanding of functional and test (DFT) mode constraints for place and route, floorplanning, power planning, IR drop analysis, cell placement, multi-mode & multi-corner (MMMC) clock tree synthesis, routing, timing optimization and closure, RC extraction, signal integrity, cross talk noise and delay analysis, debugging timing violations for MMMC designs, implementing timing fixes and functional ECOs, debugging and fixing physical violations, and formal verification. The individual also should have deep knowledge on scripting and software languages including Python, PERL/TCL, Linux/Unix shell and C. This individual will design, verify, and deliver complex Physical Design solutions from netlist and timing constraints to the final product.
Preferred Qualifications2 -10+ years industry experience
in the following areas:
-
Physical Design
-
Place & Route tool experience on Cadence Innovus and/or Synopsys Fusion Compiler
-
Timing closure experience in Synopsys PTSI
-
Formal verification experience
-
Power domain analysis experience
-
Physical verification experience
Minimum Qualifications:
- Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. OR
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).
To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.
EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.
Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.
Pay range and Other Compensation & Benefits:
$140,000.00 - $229,800.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.
If you would like more information about this role, please contact Qualcomm Careers.
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Qualcomm 소개

Qualcomm
PublicInventing the technologies the world loves.
10,001+
직원 수
San Diego
본사 위치
$136B
기업 가치
리뷰
3.7
10개 리뷰
워라밸
2.8
보상
3.5
문화
3.2
커리어
3.8
경영진
2.5
65%
친구에게 추천
장점
Good benefits and compensation
Challenging and interesting work
Great team and colleagues
단점
Management and leadership issues
Work-life balance concerns
Toxic culture/micromanagement
연봉 정보
21개 데이터
Mid/L4
Mid/L4 · Analog Mixed Signal Design Engineer
4개 리포트
$155,284
총 연봉
기본급
$119,434
주식
-
보너스
-
$155,284
$155,284
면접 경험
9개 면접
난이도
2.6
/ 5
소요 기간
14-28주
면접 과정
1
Application Review
2
Recruiter Screen
3
Technical Phone Screen
4
Onsite/Virtual Interviews
5
Team Matching
6
Offer
자주 나오는 질문
Coding/Algorithm
Technical Knowledge
System Design
Behavioral/STAR
Past Experience
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