Company:

Qualcomm India Private Limited:

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:Job Responsibilities

· STA Setup & Signoff: Perform STA setup, convergence, reviews, and signoff for multi-mode, multi-voltage domain designs for So

C & Sub System:

· Timing Analysis & Debug: Validate and debug timing across multiple PVT conditions using tools like Prime Time and Tempus.

· Flow Optimization: Run STA flows and correlate Spice to STA results.

· Methodology Development: Evaluate timing methodologies/tools across technology nodes and automate STA/PD flows using TCL/Perl/Python.

· Cross-Functional Collaboration: Work closely with design, DFT, synthesis, technology, CAD and physical implementation teams.

· Low-Power Techniques: Knowledge of clock gating, power gating, and multi-voltage designs.

· ECO Timing Flow: Handle timing ECOs (DMSA, tweaker, Prime Closure) and logical equivalence checks (RTL to Netlist). careers.qualcomm.com, careers.qualcomm.com

**Required Skills.**10+ yrs of relevant experience

· Strong expertise in STA fundamentals, AOCV/POCV concepts, CTS, and timing constraints.

· Hands-on experience with STA tools: Prime Time,Tempus.

· Familiarity with ASIC back-end flows: ICC2,Innovus.

· Knowledge of signal integrity, cross-talk noise, and parasitic extraction.

· Scripting proficiency: TCL,Perl,Python.

· Mentoring junior engineers in different areas of timing flows and methodologies

· Understanding of Spice simulations: Hspice,Fine Sim, Monte Carlo analysis.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR
  Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.
  OR
  PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

Preferred Experience:

· Driving timing convergence at chip-level and hard-macro level.

· Exposure to RTL-to-GDSII flows.

· Good technical writing and communication skills for cross-team collaboration

· Education:

B.Tech/M.Tech/MS in Electrical/Electronics/Microelectronics/VLSI.

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