Company:

Qualcomm Atheros, Inc.

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

Join Qualcomm’s Connectivity functional verification team to drive pre-silicon verification and post-silicon bring-up of high-performance RFICs for Wi-Fi, BT, UWB, FM, GNSS, and IoT applications. This role emphasizes integrating AI/ML into traditional verification workflows to accelerate design cycles and improve quality.

Required for this Role:

• Bachelor’s degree in Electrical Engineering with 3+ years of experience in RF/Analog circuit design for wireless products (e.g., LNAs, PLLs) and 4+ years in ASIC design, verification, or related work.

• OR Master’s degree in Electrical Engineering or related field with 4+ years of ASIC design/verification experience.

• OR PhD in Electrical Engineering or related field with 2+ years of ASIC design/verification experience.

• 2+ years of experience using tools such as CADENCE, Virtuoso, ADS.

• 1+ years of experience applying AI/ML techniques to circuit modeling, simulation, or verification workflows.

Responsibilities

• Develop and debug behavioral models for event-driven and mixed-signal simulation based on analog circuit design.

• Create verification plans for radio and IP modules interfacing with SoC.

• Build self-checking test benches and define test coverages and sequences.

• Maintain scripts for netlist release and programming instruction generation.

• Diagnose failed tests and manage bug tracking and resolution.

• Contribute to methodology development, especially in AI/ML-enhanced verification flows.

• Apply ML models to predict boundary values and optimize test coverage early in the design cycle.

Skills/Experience

• Strong understanding of RF-analog and digital logic design.

• Proficient in System Verilog, Python, Perl, C-Shell, and Cadence SKILL.

• Experience with Cadence AMS/XCelium tools.

• Familiarity with serial bus interfaces, register controllers, and state machines.

• Knowledge of RF transceiver architectures, PLLs, ADCs, DACs.

• Experience with UVM and functional verification of RF/mixed-signal chips.

• AI/ML Fundamentals: Understanding of supervised/unsupervised learning, neural networks, and ML-based optimization.

• Experience with ML libraries such as Tensor Flow, Py Torch, Scikit-learn, and EDA-specific ML tools.

• Ability to tailor ML models to analog/RF design topologies and verification tasks.

• Experience with Prompt Engineering for AI/ML model interaction and optimization.

Education

Master’s degree or higher in Electrical Engineering, Computer Engineering, or Computer Science preferred. Coursework or thesis in Analog/RF/Mixed-Signal Design and Machine Learning is a strong plus.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience. OR
  Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
  OR
  PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

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Pay range and Other Compensation & Benefits:

$181,700.00 - $272,500.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.

If you would like more information about this role, please contact Qualcomm Careers.