Company:

Qualcomm Atheros, Inc.

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

As a Senior Design Verification Engineer, you will contribute to ASIC verification efforts for IPs, subsystems, and So Cs used across Qualcomm’s Wi‑Fi, connectivity, and IoT platforms. You will collaborate closely with SoC architects, design, software, and validation teams to verify IPs that meet power, performance, and area goals. Additionally, you will help define and improve verification processes, methodologies, and tools for large, complex IPs and subsystems.

Job Responsibilities

• Verify IPs, subsystems, and So Cs used across Qualcomm Wi‑Fi, connectivity, and IoT platforms

• Explore and apply innovative design verification methodologies, including simulation, formal verification, and emulation, to continuously improve testbench quality and efficiency

• Own end‑to‑end low‑power verification, including testbench architecture, test plan development, and coverage‑driven verification closure

• Collaborate with cross‑geography teams on IP, SoC, and verification infrastructure deliveries, including milestone planning and critical debug activities

• Serve as a technical point of contact for IP and SoC design teams, providing verification guidance and support

• Work closely with cross‑functional stakeholders to ensure the delivery of high‑quality, robust IPs to SoC product teams

Required Skillset

• 3+ years of practical ASIC design verification experience, including ownership of verification for complex SoC subsystems or IP blocks

• Strong experience across digital design verification, including test automation, constrained‑random testing, code and functional coverage, System Verilog assertions (SVA), and performance verification

• Proven expertise in System Verilog and UVM‑based verification methodologies, including assertion‑based and coverage‑driven verification

• Strong analytical, debugging, and problem‑solving skills, with the ability to lead complex technical investigations

• Experience with C/C++ and assembly language, particularly for test development, modeling, or debug

• Solid understanding of AMBA bus protocols (e.g., AXI, AHB, APB)

• Knowledge of low‑power design concepts and power management techniques is a strong plus

• Experience with gate‑level simulation (GLS) and timing‑aware verification is a plus

• Proficiency in scripting languages such as Python and/or Perl for automation and productivity

• Strong communication skills and the ability to work effectively as part of a global, cross‑functional team

• Demonstrated leadership skills, with the ability to mentor junior engineers and drive verification best practices

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. OR
  Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
  OR
  PhD in Science, Engineering, or related field.

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Pay range and Other Compensation & Benefits:

$126,700.00 - $190,100.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.

If you would like more information about this role, please contact Qualcomm Careers.