Company:

Qualcomm Semiconductor Limited:

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

We are seeking a highly motivated Memory Layout Engineer to join Qualcomm memory design team. This role focuses on the physical implementation of memory IPs, including SRAM, ROM, and other custom memory architectures. The ideal candidate will have hands-on experience in transistor-level layout and a strong understanding of memory design principles.

Responsibilities:

• Develop transistor-level layouts for memory bitcells, sense amplifiers, and peripheral circuits.
• Collaborate closely with circuit designers to optimize layout for performance, area, and yield.
• Familiar with memory design rules; provides layout guidance and consulting to memory designers.
• Work independently to drive layout tasks from specification to tape-out with minimal supervision.
• Support memory compiler development and array-level layout integration.
• Perform layout verification and debugging using industry-standard tools.
• Stay updated on process technology changes and incorporate best practices into layout design.
• Work with cross-functional teams including design, verification, and mask preparation.

Qualifications:

• Bachelor's or Master's degree in Electrical Engineering or related field.
• 2+ years of experience in custom layout design, preferably in memory IP.
• Proficiency in layout tools such as Cadence Virtuoso or Synopsys Custom Compiler.
• Solid understanding of CMOS device physics and memory architecture.
• Familiarity with advanced process nodes (e.g., 5nm, 3nm, and below) is required.
• Experience working as a layout consultant or in close collaboration with memory designers.
• Ability to work independently and take ownership of layout tasks.
• Strong self-learning ability and initiative in mastering new technologies and workflows.
• Scripting skills in TCL or Python are a strong plus.
• Strong communication and teamwork skills.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. OR
  Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
  OR
  PhD in Science, Engineering, or related field.

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