Senior Principal Design Engineer
About the role
The candidate shall be responsible for:
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SoC u-Architecture for Clocking, Reset, Core & Interconnects, Power Management, Debug & Trace, Functional Safety, Security, IP/Subsystems integration etc.
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SoC RTL Integration using state-of-the-art tools, flows & methodologies
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LINT/CDC/RDC signoffs for the highest design quality
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Handoff checks including Verification smokesuite and express Synthesis
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Continuous learning using 3X5 Why based Root cause analysis, DFMEA, Lessons Learned for the product family
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Requirements management and traceability including IS026262 / CMMi and other compliance requirements, working closely with System Architects, Applications, Design & Verification teams, Product & Test engineering, PMO and support functions
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Overseeing technical documentation in close collaboration with information development team
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Conducting IP Integration reviews, BE reports reviews for concurrent engineering
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Driving key SoC design methodologies in close collaboration with global cross functional functional teams, Design Enablement etc.
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Mentoring other engineers based on deep core competence and expertise
Soft skills expected:
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Excellent collaboration skills and team work
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Excellent verbal & written communication skills
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Excellent presentation skills
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Passion and can-do attitude
Benefits and perks
•Learning Budget
•Flexible Hours
•401(k)
•Paid Time Off
•Vision Insurance
About NXP Semiconductors
2 Locations
Headquarters