招聘
Key Responsibilities
Custom Analog Layout Execution
- Perform full‑custom analog layout for critical circuit blocks, including:** Analog Front Ends (AFEs)**
- ADCs and DACs
- PLLs and clocking circuits
- Voltage regulators and references
- Analog filters and bias circuits
- Translate schematics into high‑quality, silicon‑proven layouts in advanced nodes.
- Apply best‑in‑class techniques for:Matching and symmetry
- Parasitic control
- Noise isolation and substrate coupling mitigation
- EM/IR and reliability robustness
Verification & Sign‑off
- Run and debug DRC, LVS, ERC, and reliability checks.
- Work with designers to close LVS and performance issues.
- Support PEX extraction and simulation correlation.
- Ensure layouts meet foundry design rules and sign‑off requirements.
Collaboration & Production Support
- Partner closely with analog circuit designers, CAD, and methodology teams.
- Participate in layout and design reviews.
- Support silicon bring‑up, debug, and yield improvement as needed.
- Contribute to layout guidelines, documentation, and best practices.
Required Qualifications
Education
- BSEE or equivalent in Electrical / Electronics Engineering (preferred).
Experience
- 6–10 years of hands‑on experience in custom analog / mixed‑signal layout.
- Proven experience working in 28nm, 22nm, and/or 16nm CMOS process technologies.
- Demonstrated experience laying out complex analog IP blocks (AFE, ADC, DAC, PLL, regulators).
Tools & Methodologies
- Strong proficiency with:** Cadence Virtuoso Layout Suite**
- Calibre (DRC, LVS, PEX)
- Solid understanding of:Foundry design rules
- Device matching and layout‑dependent effects
- Parasitics, coupling, and noise mitigation
- Reliability (EM, IR, ESD awareness)
- Familiarity with advanced-node layout challenges is required.
Preferred Qualifications
- Experience in automotive or high‑reliability semiconductor products.
- Familiarity with low‑noise, high‑speed analog layouts.
- Ability to mentor junior layout engineers.
- Exposure to ISO / automotive quality flows is a plus.
More information about NXP in Malaysia...
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关于NXP Semiconductors
NXP Semiconductors
PublicNXP Semiconductors produces secure connectivity solutions for embedded applications.
10,001+
员工数
Eindhoven
总部位置
$45B
企业估值
评价
3.7
10条评价
工作生活平衡
3.8
薪酬
4.0
企业文化
4.2
职业发展
3.2
管理层
3.0
72%
推荐给朋友
优点
Supportive management and colleagues
Good work-life balance and flexible hours
Innovation and interesting technology projects
缺点
Limited career advancement and training opportunities
Management communication and organization issues
Heavy workload and long hours during deadlines
薪资范围
227个数据点
Junior/L3
L3
Intern
Junior/L3 · Data Scientist
0份报告
$114,000
年薪总额
基本工资
$99,000
股票
-
奖金
$15,000
$96,900
$131,100
面试经验
42次面试
难度
3.1
/ 5
时长
14-28周
录用率
33%
体验
正面 69%
中性 13%
负面 18%
面试流程
1
Phone Screen
2
Technical Interview
3
Hiring Manager
4
Team Fit
常见问题
Technical skills
Past experience
Team collaboration
Problem solving
新闻动态
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3d ago
This NXP Semiconductors Analyst Turns Bearish; Here Are Top 5 Downgrades For Friday - Benzinga
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4d ago