採用
Overview:
Power integrity and signal integrity simulations become increasingly important with smaller technology nodes in system-on-chip electronic designs.Abstracted simulation models are needed, which still deliver realistic response on analog-like current demand patterns.
In this work the limits of existing modeling and simulation methods for power integrity and signal integrity depending on
modeling methods and feasible simulation complexity should be investigated and stretched out.
How far is the idea of a “digital twin” simulation combining electrical, electro-thermal, and electro-magnetic effects already feasible in SoC design?
Your tasks:
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Create an overview of existing state-of-the-art modeling methods and simulation tools for power-integrity and signal-integrity, their focus areas, and limits.
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Characterize the limitations of the modeling methods and tools, related to modeling style, simulation methods, and computational feasibility.
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Investigate the options to stretch the boundaries of modeling precision and computational feasibility,like simulation focus dependent model optimization or partitioning of simulations.
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Create a system-level simulation, which integrates IC, package, and PCB simulation for a state-of-the-art SoC focusing on power integrity and signal integrity.
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Assess the gaps existing between simulation results and reality to rate the quality of simulations as “digital twin” as well as options to close such gaps.
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Participate in the dissemination and exploitation of the results (e.g. scientific publications).
Education and Requirements:
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Master’s degree in Electrical Engineering or Technical Computer Science or related fields
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Experience with or a good understanding of SoC design methods, covering analog and digital design
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Circuit simulations experience on different integration levels, covering analog and digital design
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Strong interest in modeling and simulation methods
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Interest in pre- and post-silicon analysis (simulation and laboratory measurements)
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Fluent in spoken and written English
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Excellent communication and presentation skills (internally and externally)
The contract is part-time (80%), limited to 3 years.
Please note: The successful candidate may/will be responsible for security related tasks. The assignment may/will be in scope of security certifications, therefore a conscious and reliable way of working is necessary.
More information about NXP in Germany...
総閲覧数
1
応募クリック数
0
模擬応募者数
0
スクラップ
0
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NXP Semiconductorsについて
NXP Semiconductors
PublicNXP Semiconductors produces secure connectivity solutions for embedded applications.
10,001+
従業員数
Eindhoven
本社所在地
$45B
企業価値
レビュー
3.7
10件のレビュー
ワークライフバランス
3.8
報酬
4.0
企業文化
4.2
キャリア
3.2
経営陣
3.0
72%
友人に勧める
良い点
Supportive management and colleagues
Good work-life balance and flexible hours
Innovation and interesting technology projects
改善点
Limited career advancement and training opportunities
Management communication and organization issues
Heavy workload and long hours during deadlines
給与 レンジ
227件のデータ
Junior/L3
L3
Intern
Junior/L3 · Data Scientist
0件のレポート
$114,000
年収総額
基本給
$99,000
ストック
-
ボーナス
$15,000
$96,900
$131,100
面接体験
42件の面接
難易度
3.1
/ 5
期間
14-28週間
内定率
33%
体験
ポジティブ 69%
普通 13%
ネガティブ 18%
面接プロセス
1
Phone Screen
2
Technical Interview
3
Hiring Manager
4
Team Fit
よくある質問
Technical skills
Past experience
Team collaboration
Problem solving
ニュース&話題
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