トレンド企業

NXP Semiconductors
NXP Semiconductors

Leading company in the semiconductor industry

Senior Analog Validation/Characterization Engineer

職種エンジニアリング
経験シニア級
勤務地San Jose (Holger Way), United States
勤務オンサイト
雇用正社員
掲載1ヶ月前
応募する

必須スキル

Python

We are looking for a mid-level Mixed-Signal Engineer to join our Automotive Semiconductor division. This role bridges the gap between pre-silicon design and post-silicon reality. You will spend roughly 50% of your time developing behavioral models to speed up chip simulation and 50% of your time in the lab performing hands-on validation of high-speed transceiver silicon.

Key Responsibilities

  • AMS Modeling: Create and maintain behavioral models (System Verilog/RNM, Verilog-A) for mixed-signal blocks to support full-chip functional verification.

  • Hardware Validation: Perform bench-top characterization of high-speed transceivers (10G+) using standard lab equipment (Oscilloscopes, VNAs, BERTs).

  • Python Scripting: Develop and optimize Python scripts to automate lab measurements, parse large datasets, and generate validation reports.

  • Simulation: Run mixed-signal co-simulations (Cadence Virtuoso/Spectre) to verify connectivity and basic functionality of analog-digital interfaces.

  • Cross-Functional Support: Collaborate with Design and Verification teams to debug silicon issues and correlate lab results with simulation data.

Skills & Qualifications

  • Education: BSEE or MSEE with 3+ years of experience in IC modeling, design, or validation.

  • Simulation Tools: Experience with Cadence Virtuoso, Spectre, or similar mixed-signal simulation environments.

  • Modeling Languages: Proficiency in System Verilog(Real Number Modeling preferred) or Verilog-A.

  • Test & Measurement: Hands-on experience with high-speed lab equipment for signal integrity and performance testing.

  • Software/Scripting: Strong Python skills for automation (knowledge of libraries like Num Py, Matplotlib, or PyVISA is a plus).

Preferred Qualifications

  • Familiarity with high-speed serial standards (e.g., Ser Des, Ethernet, or PCIe).

  • Experience working within a structured Product Development Process (PDP) in a large-scale semiconductor environment.

  • Understanding of basic signal integrity concepts (jitter, eye diagrams, insertion loss).

The base salary range for this position is as mentioned below per year. We also provide competitive benefits, incentive compensation, and/or equity for certain roles.
Company benefits include health. dental, and vision insurance. 401(k), and paid leave. Please note that the base salary range (OR hourly rate) is a guideline, and individual total compensation may vary based on a number of factors such as qualifications, skill level, work location, and other business and organizational needs. This base pay range is specific to California and is not applicable to other locations. A reasonable estimate of the base salary range as of the date of this posting is:

$166,200 to $228,500 annually

More information about NXP in the United States...

NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.

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NXP Semiconductorsについて

NXP Semiconductors

NXP Semiconductors produces secure connectivity solutions for embedded applications.

10,001+

従業員数

Eindhoven

本社所在地

$45B

企業価値

レビュー

10件のレビュー

3.7

10件のレビュー

ワークライフバランス

3.5

報酬

4.0

企業文化

3.8

キャリア

3.2

経営陣

3.0

72%

知人への推奨率

良い点

Supportive management and colleagues

Innovation and interesting technology

Good work-life balance and flexible hours

改善点

Management issues and poor communication

Limited career advancement and training

Heavy workload and long hours

給与レンジ

227件のデータ

Junior/L3

Intern

L3

Junior/L3 · Data Scientist

0件のレポート

$114,000

年収総額

基本給

$99,000

ストック

-

ボーナス

$15,000

$96,900

$131,100

面接レビュー

レビュー42件

難易度

3.1

/ 5

期間

14-28週間

内定率

33%

体験

ポジティブ 69%

普通 13%

ネガティブ 18%

面接プロセス

1

Phone Screen

2

Technical Interview

3

Hiring Manager

4

Team Fit

よくある質問

Technical skills

Past experience

Team collaboration

Problem solving