Team leadership for photolithography process engineering. Focus areas include process sustaining for the 24x7 operation, development, qualification, and release of improved photo-lithography processes on both existing and new technology generations.

Support the execution of a steep wafer volume and yield roadmap in the existing manufacturing wafer fab (Fab1).

Team leadership related to process qualification and implementation in a new fab focusing on larger wafer sizes (Fab2).

Participate in various cross functional teams as a technical content expert.

• JMP, DOE, SPC

• Working knowledge of semiconductor fabrication processes, and specific expertise in photo-lithography.

• Strong leadership and communication skills.

• Experience with semiconductor process development, sustaining, new process introduction, and ramp to volume.

• Experience supporting a 24x7 fab operations team, writing and training of fab procedures, root cause analysis and problem resolution.

Education/Experience Required:

BS with 5 years’ experience, or MS with 3 years’ experience.

• Optimize coat, exposure and develop processes related to Indium Phosphide (InP) based Photonic Integrated Circuit (PIC) wafer fabrication. Develop and implement processes with improved process capability in both Fab1 and Fab2.

• Develop and deploy control plans to keep photo-lithography processes operating within performance parameters.

• Troubleshoot photo-lithography process problems and drive details of improvement project execution to enable a smooth flow of production and development wafers.

• Execute process development and lithography roadmap activities needed for future PIC technology.

• Participate in various cross functional teams consisting of equipment, process, and integration engineers to improve process capability, wafer yields, simplify procedures and processes, and release new tools and processes with improved capacity and capability.

• Maximize the opportunity to adopt semiconductor industry best practices for Fab2 including automation of wafer and reticle handling and releasing more modern manufacturing tools for PIC wafers with variable topography.

• Lead team members partnering with the PIC R&D team to enable the development and qualification of new processes required to deliver next generation high-performance multi-Tb PICs.