Principal ASIC Design Engineer

Experience with low-power ASIC design techniques and clock domain crossing

• Knowledge of AMS verification methodologies

• Exposure to silicon bring-up and lab validation

• Familiarity with EDA tools from Synopsys, Cadence, or Mentor

• Bachelor’s or Master’s degree in Electronics Engineering, Computer Engineering, or related field

• 8+ years of experience in ASIC digital design, with couple of years of technical leadership role

• Strong expertise in RTL design, CDC, synthesis, STA, LEC..

• Proven experience in mixed-signal ASICs for deep sub-micron and understanding of analog-digital interfaces

• Familiarity with any scripting languages

• Excellent problem-solving, communication, and leadership skill

Key Responsibilities

• Lead the architecture, design, and verification of digital blocks for mixed-signal ASICs

• Collaborate closely with Analog and System teams to define specifications and ensure seamless integration

• Drive RTL design using Verilog/System Verilog and optimize for power, performance, and area

• Follow the digital design flow from concept to tape-out, including synthesis, static timing analysis etc..

• Guide and mentor digital designers and verification engineers

• Interface with backend teams for physical design and support post-silicon validation

• Contribute to IP reuse strategy and design methodology improvements

• Participate in design reviews and provide technical leadership across cross-functional teams