Nokia's Optics Subsystems group develops the front-ends for coherent optical long-distance transmission modules to interconnect network nodes and data centers. We are expanding and looking for highly motivated and experienced engineers to join us to develop the next generations of transmission systems.

Within Optics Subsystems, the SoC (System-on-Chip) team members architect, specify, design and test the ASICs (Application-Specific Integrated Circuit) for the optical modules. Our main goal is to extend the optical reach and transmission bandwidth and at the same time reduce the power and floorspace needs by using the latest chip technologies.

As FEC (Forward Error Correction)\ASIC (Application-Specific Integrated Circuit) Engineer you will contribute to soft‑decision FEC (Forward Error Correction) modelling, implementation, and verification for coherent optical modems at >800 Gbit/s, developing ASIC‑ready algorithms.

Sounds interesting?
Be sure to check out details about our latest ASIC\SoC development, in the Optical Engines page:
https://www.nokia.com/networks/optical-networks/pse-6s/ and ICE-X 800G ZR/ZR+ | Nokia.com.

Must have:

• Master’s or Ph.D. in Electrical Engineering, Computer Engineering, or related field; exceptional Bachelor’s with relevant internships considered.
• Foundational knowledge across: Binary BCH, Reed‑Solomon, Turbo Product codes (BCH components), Binary LDPC (regular/irregular/spatially coupled), Staircase codes, CFEC, OFEC.
• Practical experience in MATLAB, C, and C++; ability to write clear, well‑tested numerical code.
• Strong analytical skills, collaborative mindset, independent work ethic, and effective communication.
• Due to cross-location collaborations, the candidate must be fluent in English. Knowledge of German and/or Italian is a plus.

Nice to have:

• Hands‑on FEC (Forward Error Correction) design with proven delivery (tape‑outs, deployed systems).

• Exposure to ASIC (Application-Specific Integrated Circuit) concepts (parallelism, fixed‑point arithmetic, high‑throughput design) via coursework or internships.

• Familiarity with scripting/automation (Python), version control (Git), and basic FPGA/emulation flows.

• Contribute to the design, implementation and validation of soft‑decision FEC (Forward Error Correction) algorithms (10%–50% overhead) targeting near‑capacity performance in >800 Gbit/s coherent links.

• Develop simulation environments and testbenches; characterize BER (Bit Error Rate)/FER (Frame Error Rate) vs. SNR (Signal-to-Noise Ratio) and optical impairments; compare against golden models.

• Contribute to defining fixed‑point formats, quantization strategies, parallel/pipelined decoder architectures, and memory organization for ASIC (Application-Specific Integrated Circuit) realization.

• Collaborate closely with ASIC (Application-Specific Integrated Circuit) teams to translate algorithms into robust modem implementations, in generation of test vectors and supporting hardware/software co‑verification.