
Limited company.
SoC/FPGA Engineer
Required skills
Python
Linux
The NOKIA Optics Subsystems group develops the front-ends for coherent optical long-distance transmission modules to interconnect network nodes and data centers. We are expanding and looking for highly motivated and experienced engineers to join us to develop the next generations of transmission systems.
Within Optics Subsystems, the SoC (System-on-Chip) team members architect, specify, design and test the ASICs for the optical modules. Our main goal is to extend the optical reach and transmission bandwidth and at the same time reduce the power and floorspace needs by using the latest chip technologies.
Sounds interesting?
Be sure to check out details about our latest ASIC\SoC development, in the Optical Engines page:
https://www.nokia.com/networks/optical-networks/pse-6s/
Must have:
- Strong knowledge of DSP theory and algorithms, including modulation formats, equalization techniques, and error correction coding.
- Strong knowledge and practical experience about ASIC and FPGA design and verification, respective implementation tools (Synopsys, Mentor, Cadence), the related design languages (VHDL, Verilog, System Verilog), script programming (TCL, Python) and overall development environment
- Proven experience in Formal Verification of design results (e.g. LEC, CDC, PDV) as well as use of hardware emulators
- Basic understanding of firmware development, software structures and methods (C/C++, development of drivers and APIs for the design blocks)
- Good communication skills, fluent written and spoken English (required), with a strong interest to collaborate with international partners.
It would be beneficial if you also had:
- Inter-disciplinary and inter-cultural collaboration experience
- Knowledge in LINUX-based systems IT infrastructure management
- Knowledge in ASIC Design verification methodologies (e.g. UVM)
- Knowledge about optical transmission standards like OIF, IEEE, ITU-T etc.
- Knowledge about coherent optical transmission systems and their components, transmission theory and algorithms, forward error correction, modulation formats and their implementation
The position requires a Master’s degree or PhD in Electronic Engineering, Microelectronics, Telecommunication Engineering or equivalent.
As ASIC engineer involved in the architecture and development of sub-micron devices, your development tasks are highly demanding in technical and soft skills. You will be working in a culture of autonomy and individual responsibility as part of an international development team, building system-on-chip devices for coherent transmission systems.
This position is especially focused on DSP design for Coherent Transmission ASIC devices
- Highly skilled ASIC Development Specialist with expertise in Coherent Transmission DSP.
- Proficient in developing complex ASIC designs and IP for optical communication systems, utilizing advanced signal processing algorithms.
- Experienced in RTL design, verification, synthesis, and physical implementation, ensuring high-performance and low-power ASIC solutions.
- Implement RTL (Register Transfer Level) to gate-level netlist synthesis using industry-standard tools, collaborating closely with the design and verification teams.
- Stay current with industry trends and advancements in ASIC synthesis methodologies.
- Investigate and optimize power consumption by leveraging on latest CMOS technology nodes and applying dedicated power analysis tools and techniques
- Collaborate with cross-functional teams systems engineering, hardware, software and firmware development teams and test engineering in international Nokia locations
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About Nokia

Nokia
PublicNokia Corporation is a Finnish multinational telecommunications, information technology, and consumer electronics corporation, originally established as a pulp mill in 1865.
10,001+
Employees
Espoo
Headquarters
$24B
Valuation
Reviews
10 reviews
3.8
10 reviews
Work-life balance
3.7
Compensation
3.2
Culture
4.1
Career
2.8
Management
3.4
72%
Recommend to a friend
Pros
Good benefits
Supportive colleagues/management
Flexible work arrangements
Cons
Limited career advancement/growth opportunities
Management issues (poor communication, lack of direction)
Long hours/high workload
Salary Ranges
28 data points
Junior/L3
Mid/L4
Junior/L3 · Global 1830 TAC Engineer
1 reports
$141,314
total per year
Base
$108,703
Stock
-
Bonus
-
$141,314
$141,314
Interview experience
4 interviews
Difficulty
3.0
/ 5
Duration
14-28 weeks
Offer rate
25%
Experience
Positive 50%
Neutral 25%
Negative 25%
Interview process
1
Application Review
2
Recruiter Screen
3
Technical Interview
4
HR Follow-up
5
Offer
Common questions
Technical Knowledge
Coding/Algorithm
Behavioral/STAR
Past Experience
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