Overview:

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, One Drive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for a Principal Physical Design Engineer to help achieve that mission.

The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantage to Microsoft and enable our customers to achieve more.As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, Microsoft’s Compute Silicon & Manufacturing Engineering team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware.We are looking for a Principal Physical Design Engineer with a passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.

We are looking for a Principal Physical Design Engineer to join the team.

• Responsibilities- Responsible for SOC Top Level Design Planning and partitioning strategies.
• Responsible for RTL to GDS implementation in Physical Design domain.
• Coordinate with CAD, RTL/Design teams/DFT, Architecture team, Power & Performance team, Technology team & other internal/external partners as essential.
• Lead & influence design tools, flows, and methodologies in construction, signoff, and optimization through a data-driven approach.
• Lead and manage floor-planning and design planning activities to optimize timing-critical and large sub-chips for power, performance, and area (PPA).
• Drive end-to-end execution from synthesis through place-and-route for large designs, ensuring completion of all signoff stages including timing, physical verification, EMIR, formal equivalence, and low-power verification.
• Develop guidelines, checklists, and best practices for top-level physical design..
• Make sound technical trade-offs between power, area, and timing to achieve optimal design outcomes.
• Foster collaboration across teams to deliver the best possible solutions, aligned with a One Microsoft mindset.
• Demonstrate technical expertise across various domains of Physical Design & Timing Signoff.
• Clear communications on project status & planning.
• Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion.

Qualifications:

Required Qualifications:

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.

Other Requirements:

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.Preferred Qualifications:

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 12+ years technical engineering experience OR equivalent experience.
• 1+ year(s) experience working on or leading projects from beginning-to-end.
• Experience in SOC Top Level work, Design Planning and integration with multiple production tape-outs using advanced foundry process nodes.
• Demonstrate technical expertise in all aspects of Physical Design, from synthesis to place and route of partitions through all signoff including timing signoff, physical verification, EMIR signoff , Formal Equivalence, and Low Power Verification.
• Own complete PD execution of Critical blocks/Partitions/Sub-systems/Sub-chips instantiating/integrating multiple other Physical partitions. Be fully hands-on in your individual ownerships as individual contributor and collaborate cross-team as required.
• Proficient in integration activities and design planning (DP) methodology with hands-on experience.
• Good understanding of timing constraints (functional & DFT), static timing analysis (STA), and timing-power optimization.
• Thorough understanding of SOC or subsystem design trade-offs across power, performance, and area (PPA).
• Hands-on experience with clock tree synthesis (CTS) and global clock distribution in complex multi-voltage, multi-clock, multi-domain, and low-power designs.
• Partner closely with PD flow/CAD team and PD methodology team to flag & fix PD TFM issues upfront and ensure those are fixed in the next PD TFM release from CAD or are updated in the design project layer (as appropriate).
• Skilled in industry-standard EDA tools (Synopsys or Cadence).
• Mentor junior engineers on technical aspects.
• Advanced proficiency in Engineering Change Order (ECO) implementation for power and timing convergence, with solid knowledge of functional and DFT ECO closure methodologies.
• Demonstrated ownership of deliverables and strong cross-functional teamwork.
• Experience in mentoring, influencing teams, and driving alignment through clear and effective communication.
• Good analytical and problem-solving skills, complemented by advanced scripting capabilities in Perl, TCL, and Python.
  #SCHIE #CSME

Silicon Engineering IC5 - The typical base pay range for this role across the U.S. is USD $139,900 - $274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
https://careers.microsoft.com/us/en/us-corporate-pay

This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.