CAD and Integration Engineer, Silicon

We are looking for a CAD and Integration Engineer to join our custom silicon team. Working in close partnership with circuit designers, digital designers and layout engineers, you will translate circuit intent into physical constraints, drive synthesis, place-and-route, and signoff, and bridge the gap between schematic and silicon. You will also play a key role in enabling 3D stacking flows between heterogeneous process nodes. Beyond implementation, we expect a builder's mindset: developing automation tools, improving CAD flows, and actively leveraging AI-assisted design to increase team-wide engineering velocity.
CAD and Integration Engineer, Silicon Responsibilities
Integrate AI/LLM tools into workflows to drive design automation and engineering productivity
Lead analog mixed signal physical integration and enforce design constraints in collaboration with design and layout teams
Manage end-to-end digital implementation flows (RTL-to-GDS), including synthesis, PNR, DFT insertion, and signoff
Drive physical signoff (timing, power, verification) to ensure foundry-ready deliverables
Develop 3D stacking flows for heterogeneous integration and die-to-die interface planning, cross-die timing and power analysis
Automate implementation, tapeout, and regression using Python, SKILL, and Tcl

Minimum Qualifications:

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
BS/MS/PhD in EE, CE, or a related field with 12+ years of industry experience
Proven industry experience in analog CAD/automation support areas involving various technology nodes and tapeouts
Expertise in full RTL-to-GDS flow, digital synthesis, PNR, and physical signoff
Proficiency in analog mixed signal design environment and simulation tools

Knowledge of PDK and Spice model qualification:

Strong programming skills in languages such as SKILL, Python, Perl etc. to provide automation needs
Hands-on experience with AI coding assistants
Experience communicating technical decisions and project status to cross-functional partners, including circuit designers, layout engineers, and foundry contacts

Preferred Qualifications:

Familiarity with advanced packaging technologies and their implications for chip-level CAD methodology and integration flows
Experience with hierarchical chip integration and assembly flows for large, multi-block So Cs targeting consumer electronics or wearable device applications
Experience with low-power design methodologies including multi-voltage domain integration, UPF-based power intent, and power analysis sign-off for mobile or wearable silicon
Experience engaging directly with foundry partners on process design kit development, design rule updates, and technology qualification for leading-edge nodes

About Meta

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For those who live in or expect to work from California if hired for this position, please click here for additional information.
United States of America: $212,000/year to $294,000/year + bonus + equity + benefits
Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.

Equal Employment Opportunity:

Meta is proud to be an Equal Employment Opportunity employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other applicable legally protected characteristics. You may view our Equal Employment Opportunity notice here.
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