About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

As a Digital IC Design Senior Staff Engineer with Marvell, you’ll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Automotive, Storage, Security, and Networking. You’ll be part of a digital team of about eight people making a big impact on this organization, working on ultra-dense and performance Static Random Access Memory (SRAM) memory compilers.

This team hires some of the biggest problem solvers in Silicon and has a huge impact on the work done at Marvell. The customers served by this team are often other chip companies and big tech companies, familiar names to all candidates.

What You Can Expect

• Architect & Design:

Develop high-performance, low-power memory IP (SRAM, Register Files) and compiler architectures. Expect the individual to be innovative to innovate on new circuit ideas and architectures. Expect the individual to have done and lead development of all kinds of memory compilers such as 1R1W, SRAM, 2R2W, ROM etc… Expect the individual to be well versed in all aspects of memory compiler design such as circuit design of all sub blocks of memories, critical path, block wise design validation of all blocks (Sense, bitcell, Rowdec, level shifter etc..), Memory level design validation such as self time analysis, Montecarlo analysis, race check analysis etc… Expect the individual to be also aware of characterization methodology and process. Expect the individual to be well aware of all deliverables of memory compiler. Your role involves conducting in-depth circuit analysis for compact sub-circuit blocks within our overall design, considering Process, Voltage, and Temperature (PVT) factors. Using your experience using transistor-level circuit design software like Cadence Virtuoso or Spectre X for design analysis, you will be mentoring others to optimize performance within specified area and power constraints, utilizing engineering judgment to balance trade-offs and refine designs.

• PPA Optimization:

Drive design methodologies for power, performance, and area targets, Push the designs to achieve the maximum PPA targets.

• Design Validation & : The engineer will be responsible of All types of Design validation, Margin, Full instance, espcv, SA, bit cell, selftime analysis, Momtecarlo analysis.
• Characterization : The engineer will also be involved in Characterization of Memory compilers and will be responsible for views generation after the characterization and would be responsible for the validation of the characterized timings.
• Leading Edge Process-Design co-optimization for Robust design:

Expect the individual to have worked on leading edge nodes like 2nm, 3nm etc… and on GAE, Finfet & planar. Expect the individual to understand all the process complexities and build robust compilers

• Automation:

Enhance compiler flows, generators, and design libraries using scripting (Python, TCL).

• Collaboration:

Work across teams

• proficiency in a Linux environment is essential for seamless execution.

What We're Looking For

To be successful in this role, you must:

• Have a Bachelor’s or Master’s in Electrical Engineering, Electronics, VLSI Design or similar field.

• Expect the candidate to have minimum of 5 years of experience in SRAM/ROM Memory circuit design & Validation. Preferred will be 5-8 years of experience.

• Independently analyzes and optimizes small sub-circuit blocks within our overall design across Process, Voltage, Temperature

• engineer will be responsible for complete block/compiler design from architecture definition to fine tuning of all types of SRAM/ROM/RF Memory compilers

• Identifies and proposes innovative solutions to enhance the design of at least one major sub-circuit block.

• Participates in root cause investigation and silicon validation of model to hardware correlation issues.

• coaches new and/or less experienced team members.

• Tools:

Cadence Virtuoso, Synopsys tools (Design Compiler, Prime Time), HSPICE, Spectre, solido.

• Experience:

Deep sub-micron nodes (7nm/5nm/3nm), compiler IP development, foundry PDKs, memory design, validation & characterization.

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.