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About Marvell
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
The Custom Compute and Storage (CCS) Business Unit collaborates with strategic customers
to develop advanced So Cs—from architecture through production.
The Emulation Center of Excellence (CoE) plays a critical role in:
- Delivering scalable emulation infrastructure
- Enabling pre-silicon validation
- Driving software readiness and post-silicon success
In this role, you will lead and contribute to emulation of key subsystems including: - Boot and Security
- High-speed interfaces: PCIe, CXL, Ethernet
- Memory subsystems: DDR, HBM
- Low-speed peripherals: SPI, I2C, UART
- USB 3.0
What You Can Expect
- Lead the development of complex SoC emulation models, including design
integration, environment setup, compilation, and debug across industry-leading platforms
(e.g., Veloce, Ze Bu, Palladium).
- Drive emulation bring-up activities, including clock/reset sequencing, firmware boot,
and system validation using pre-silicon hardware models.
- Create and execute emulation test plans to support verification, performance
analysis, software development, and system validation needs across multiple teams.
- Collaborate closely with RTL design, verification, and firmware teams to define
requirements, develop accurate hardware models, and ensure seamless integration into
the emulation environment.
- Debug complex SoC and subsystem issues across RTL, firmware, emulation
platforms, and toolchain interactions.
- Optimize emulation performance, including model partitioning, timing, and runtime
efficiency.
- Automate flows and improve productivity through scripting (Python, Perl, Tcl, shell)
and tooling enhancements.
- Interface with EDA vendors (Synopsys, Cadence, Siemens) to evaluate tool
capabilities, resolve technical issues, and drive feature improvements.
- Define and execute emulation strategy for complex So Cs across multiple subsystems
(Boot, Security, PCIe, CXL, DDR, HBM, USB, Ethernet, and peripherals)
-
Develop and drive subsystem-level and full-chip emulation test plans
-
Enable pre-silicon validation of firmware, boot flows, and security features
-
Collaborate with cross-functional teams to bring up and debug:o PCIe / CXL link and protocol issues
o DDR / HBM initialization and performance validation
o Ethernet and USB 3.0 integration
o Low-speed peripheral functionality (SPI, I2C, UART)
- Enable firmware and software teams by providing stable and scalable emulation
environments
What We're Looking For
- Bachelor’s degree with 18+ years, or Master’s/PhD with 15+ years in Electrical
Engineering, Computer Science, or related field
- Strong experience in SoC emulation, validation, and debug
- Expertise in one or more domains:
o Boot flow and system initialization
o Security architecture and validation
o High-speed protocols: PCIe, CXL, Ethernet
o Memory interfaces: DDR, HBM
o Peripheral interfaces: SPI, I2C, UART, USB 3.0
-
Deep understanding of SoC architecture, interconnects, and system-level integration
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Hands-on experience with emulation platforms (Palladium, Ze Bu, Veloce)
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Strong debugging skills across HW/SW boundary
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Proficiency in scripting: Python, Perl, Tcl, Shell
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Proven ability to lead cross-functional efforts and drive execution
Additional Compensation and Benefit Elements
With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.
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Marvell 소개

Marvell
PublicMarvell Technology, Inc. is an American company, headquartered in Santa Clara, California, which develops and produces semiconductors and related technology.
5,001-10,000
직원 수
Santa Clara
본사 위치
$15.2B
기업 가치
리뷰
3.6
10개 리뷰
워라밸
3.2
보상
3.8
문화
3.5
커리어
2.8
경영진
2.9
62%
친구에게 추천
장점
Good benefits and compensation
Supportive team and leadership
Flexible work arrangements
단점
Limited career advancement opportunities
High workload and long hours
Poor management communication
연봉 정보
16개 데이터
Junior/L3
Junior/L3 · DATA SCIENCE AND ENGINEERING PROFESSIONAL II
1개 리포트
$111,800
총 연봉
기본급
$86,000
주식
-
보너스
-
$111,800
$111,800
면접 경험
1개 면접
난이도
3.0
/ 5
소요 기간
14-28주
합격률
100%
경험
긍정 100%
보통 0%
부정 0%
면접 과정
1
Application Review
2
Recruiter Call
3
Technical Screen
4
Final Round Interview
5
Offer Decision
자주 나오는 질문
Technical Knowledge
System Design
Behavioral/STAR
Past Experience
UI/UX Design Principles
뉴스 & 버즈
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