About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

Data Center Engineering Business Unit closely collaborates with strategic customers in the development of advanced and highly complex So Cs, from architecture and design all the way through layout, packaging, prototype validation and production ramp up. This group provides technology development, EDA/methodology development and IP/Chip design development. India DFT team is a key part of Global DFT community with global ownership and responsibility for delivering generic and more advanced custom DFT architecture solutions, methodology and design. You will be working with this team to directly enable customer DFT requirements for Custom and Compute Businesses.

What You Can Expect

• Develop and integrate scan, MBIST, OCC, boundary scan, and hierarchical SDC flows.

• Drive ATPG pattern generation, compression techniques, GLS (Gate‑Level Simulation), and retargeting.

• Collaborate with RTL, synthesis, and physical design teams to ensure seamless DFT integration.

• Perform Spy Glass DFT checks to validate design quality and testability compliance.

• Perform pre‑silicon validation of DFT features and support post‑silicon bring‑up.

• Optimize test methodologies for cost, coverage, and yield improvement.

What We're Looking For

• Bachelor’s/Master's degree in Electrical/Electronics Engineering, VLSI, or related field with 5 to 8 years of experience in DFT for complex ASIC/SoC designs.

• Strong expertise in:

Scan insertion and ATPG tools (Synopsys, Cadence, Mentor).

• MBIST/OCC validation flows.

• Hierarchical DFT and SDC constraint management.

• Solid understanding of SSN design and IEEE 1687 IJTAG standards for embedded instrumentation.

• Good understanding of Spy Glass DFT rules for design quality and testability compliance.

• Strong fundamentals in Digital Circuit Design and Logic Design.

• Good understanding of RTL design, synthesis, STA, and physical design flows.

• Hands‑on experience with scripting (TCL, Perl, Python, Shell, etc.) for automation and flow development.

• Hands‑on experience with silicon bring‑up and debug.

• Good problem‑solving, communication, and cross‑functional collaboration skills.

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.