
Leading company in the technology industry
Principal Software Engineer -memory constrained embedded C/C++ Firmware development
必須スキル
Python
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About Marvell
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
This is an existing vacancy.
Your Team, Your Impact
The Optical Digital Signal Processing (ODSP) PHY SW Team develops software for Marvell's DSP products used in pluggable optical modules—chips that form the backbone of the internet, moving data within and between data centers worldwide. Marvell is the market leader in direct-detect optical DSPs (100G to 1.6T), with products deployed in every major cloud data center and AI cluster. We own all SW components including embedded FW, customer SDK, and lab scripts, and we're the go-to group for getting things done across the entire product lifecycle—from pre-silicon simulation through field deployment.
What You Can Expect
The core responsibilities for the SW team include embedded FW that runs on our RISC-V-based multi-core MCU, C SDK provided to customers, Python-based GUI for in-field debug, and test infrastructure for the above.
The SW team is a key enabler for bringing a product to production, and the role of a Principal Engineer in our team is to ensure the overall success of that product. This role combines technical leadership with project coordination responsibilities.
Technical Leadership & Development
- Lead the Architecture, Design, Development, and Testing of embedded C firmware for controlling our extremely complicated DSP HW
- Serve as the technical lead on a product, guiding SW team members (2-8 developers) through the development process
- Drive firmware development for DSP control blocks including RX/TX signal processing, FEC, PLL/FLL, reference generation, and thermal monitoring
- Lead technical reviews of firmware architecture, API design, and system integration approaches
- Translate complex specifications from standards bodies (MSA/OIF/CMIS) or directly from customers into easy-to-digest requirements, and clear sequence diagrams to aid in development
- Take lead on difficult to debug issues, drive to root causes with HW/Systems teams, and follow up with test/validation/customer support teams
Project Coordination & Cross-Functional Collaboration
- Work with the cross-functional team to plan SW milestones, develop in sprints, closing tickets, and roll out features for the product
- Coordinate with Marketing, AE, Test, Validation, SW_QA, and Hardware teams to align on deliverables and schedules
- Provide regular status updates on milestones, scope, dependencies, and blockers
- Manage Agile sprint planning and backlog prioritization in collaboration with stakeholders
Customer Engagement & Support
- Lead technical discussions with tier-1 customers on feature requirements, API specifications, and implementation
- Support customer bring-up activities and resolve field issues
- Work with AE teams to understand customer expectations and deliver critical features
- Handle customer-specific feature development such as FEC burst statistics, VDM telemetry, and CMIS compliance
Team Development
- Mentor engineers on embedded firmware development, debugging techniques, and best practices
- Conduct code reviews and provide technical guidance to ensure code quality and maintainability
- Foster collaboration across geographically distributed teams
What We're Looking For Minimum Requirements:
- BS/MS degree in Computer Science, Electrical/Software Engineering, or related technical field(s)
- 10+ years of experience in memory constrained embedded C/C++ FW development
- SW Team Lead or Technical Lead experience on embedded projects
- Architecture design & development, code reviews & testing, through to customer volume production
- Understanding of embedded SoC, micro-controller architecture (RISC-V a plus), memory-mapped hardware interfaces, GPIOs, ISRs, etc.
- Excellent verbal and written communication skills in English, and able to collaborate in a large cross functional organization
- Excellent problem-solving and customer debug skills on real hardware in the lab
- Experience with using revision control and defect tracking systems
Preferred but not required:
- Experience with SERDES, IM-DD/Coherent DSP, Ethernet/PCIe PHYs, and/or Optical Module SW
- Experience with designing/developing/debugging software state machines, transitions, context saving, error handling
- Experience with mixed-signal (analog+digital) control and monitoring, PID/feedback loop control
- Experience with bare-metal, RTOS, device driver, Linux kernel, etc.
- Familiarity with advanced compiler options and details (clang/gcc preferred)
- Proficient in C and Python, with knowledge of git, Linux, makefiles, gdb, IDEs, bash
- Familiarity with digital verification test flows, FPGA emulation, hardware languages such as Verilog
- Familiarity with lab equipment such as oscilloscopes, supplies, PNAs, ONTs
- Understanding of Ethernet networking from the OSI model, with emphasis on the PHY up to the data link level
- Familiarity with forward error correction, PCS framing, PMA/PMD, PRBS, and other PHY traffic schemes
- Understanding of signal processing: histograms, BER, SNR, sampling phase, Shannon limit, impulse & frequency response, FFT, etc.
Expected Base Pay Range (CAD)
145,800 - 194,400, $ per annum
Additional Compensation and Benefit Elements
With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.
Marvell may employ artificial intelligence technologies to assist in the evaluation of job applications. All application reviews include meaningful human involvement, and no hiring decisions are made solely on the basis of automated processing.
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Marvellについて

Marvell
PublicMarvell Technology, Inc. is an American company, headquartered in Santa Clara, California, which develops and produces semiconductors and related technology.
5,001-10,000
従業員数
Santa Clara
本社所在地
$15.2B
企業価値
レビュー
10件のレビュー
4.0
10件のレビュー
ワークライフバランス
4.2
報酬
3.5
企業文化
4.1
キャリア
3.2
経営陣
3.4
75%
知人への推奨率
良い点
Supportive team and leadership
Good work-life balance and flexibility
Collaborative and inclusive environment
改善点
Management issues and disorganization
Limited career advancement opportunities
High workload and stress
給与レンジ
16件のデータ
Junior/L3
Junior/L3 · DATA SCIENCE AND ENGINEERING PROFESSIONAL II
1件のレポート
$111,800
年収 総額
基本給
$86,000
ストック
-
ボーナス
-
$111,800
$111,800
面接レビュー
レビュー1件
難易度
3.0
/ 5
期間
14-28週間
内定率
100%
体験
ポジティブ 100%
普通 0%
ネガティブ 0%
面接プロセス
1
Application Review
2
Recruiter Call
3
Technical Screen
4
Final Round Interview
5
Offer Decision
よくある質問
Technical Knowledge
System Design
Behavioral/STAR
Past Experience
UI/UX Design Principles
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