refresh

トレンド企業

トレンド企業

採用

求人Marvell

Principal Engineer, Hardware Systems & Silicon Validation

Marvell

Principal Engineer, Hardware Systems & Silicon Validation

Marvell

Irvine, CA

·

On-site

·

Full-time

·

2mo ago

福利厚生

Parental Leave

Learning

Flexible Hours

必須スキル

Python

JavaScript

TypeScript

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

The Post-Silicon Validation team is instrumental in designing test platforms and executing comprehensive validation processes that span functional, electrical, and system-level testing, along with firmware and software validation. The team also supports the integration of Marvell solutions into customer platforms, including Ethernet switches and Wi-Fi access points.

System Validation Engineers ensure Marvell’s connectivity products meet rigorous performance and reliability standards across enterprise, industrial, and cloud data center deployments.

What You Can Expect

  • Own responsibility for Marvell Ethernet Cu PHY Validation in post-silicon environment.
  • Develop System-level and Silicon-level test plan for Marvell Alaska-M Ethernet PHY and Alaska-C HSC Retimer PHY products.
  • Define, document, execute and report the overall PHY validation/test plan for Marvell storage devices.
  • Lab-based silicon bring-up and unit test execution focused on 10BASE-T Physical and PCS layer hardware and firmware functionality.
  • Perform high speed signal validation and analysis using various test equipment to measure Eye diagram/Jitter/BER.
  • Analyze and debug issues on PHY protocol of storage interface (SERDES, Ethernet).
  • Troubleshoot failing tests using diagnostics, software tools, hardware analyzers, oscilloscopes, meters, logic/protocol analyzers.
  • Lead collaborative technical discussions to drive resolution on technical issues. Work with cross-functional teams and external vendors to debug any post-silicon and/or customer issues related to Cu PHY and High Speed SERDES Retimer PHY.
  • Work closely with customers to address design issue and debug failure cases.

What We're Looking For

As a Principal Engineer in Hardware and Silicon Validation at Marvell, you will play a key role in the development and delivery of Marvell’s Alaska-M and Alaska-C Ethernet PHY products. Your responsibilities will include validating high-performance networking hardware, such as copper 10GBASE-T Ethernet PHYs and high-speed PAM4 SERDES retimer transceivers—critical technologies that enable high-density Ethernet switch applications across enterprise, PoE, wireless, and data center environments.

  • Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience.
  • Strong understanding of high-speed SERDES, equalization technique and Ethernet Networking protocols.
  • 5 years of experience with High Speed IO testing, Analog AFE characterization debugging and validation
  • Strong lab skills with hands on experience, in system bring up, system testing and debug.
  • In-depth working knowledge of test equipment used for PAM4 SERDES characterization and 10GBASE-T Cu PHY Ethernet AFE Analog ADC, DAC characterization (Scope, BERT, Network analyzer, Spectrum Analyser etc.).
  • Strong analytical, problem-solving and communication skills.

Preferred:

  • Working knowledge of Ethernet Networking interface and characterization.
  • Working knowledge and experience on Ethernet and PAM4 SERDES is a definite plus.
  • Extensive knowledge of the physical and protocol levels (PMA, PCS, MAC) of one or more common high-speed interfaces is an asset.
  • Working knowledge of hardware board design; able to read board schematics and board layout.
  • Working experience with Python.

Expected Base Pay Range (USD)

144,800 - 214,340, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

At Marvell, we offer a total compensation package with a base, bonus and equity.

Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOpsmarvell.com.

Interview Integrity As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, Co Pilot, or note-taking bots) during interviews.

Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

連絡先と所在地

総閲覧数

0

応募クリック数

0

模擬応募者数

0

スクラップ

0

Marvellについて

Marvell

Marvell

Public

Marvell Technology, Inc. is an American company, headquartered in Santa Clara, California, which develops and produces semiconductors and related technology.

5,001-10,000

従業員数

Santa Clara

本社所在地

$15.2B

企業価値

レビュー

3.6

10件のレビュー

ワークライフバランス

3.2

報酬

3.8

企業文化

3.5

キャリア

2.8

経営陣

2.9

65%

友人に勧める

良い点

Good benefits and compensation

Supportive team and leadership

Flexible work arrangements

改善点

Limited career advancement opportunities

High workload and long hours

Poor management and communication

給与レンジ

16件のデータ

Junior/L3

Junior/L3 · DATA SCIENCE AND ENGINEERING PROFESSIONAL II

1件のレポート

$111,800

年収総額

基本給

$86,000

ストック

-

ボーナス

-

$111,800

$111,800

面接体験

1件の面接

難易度

4.0

/ 5

期間

14-28週間

内定率

100%

体験

ポジティブ 100%

普通 0%

ネガティブ 0%

面接プロセス

1

Application Review

2

Recruiter Screen

3

Technical Phone Screen

4

Technical Interview

5

Final Round/Onsite

6

Offer

よくある質問

Technical Knowledge

System Design

Behavioral/STAR

Past Experience

UI/Frontend Architecture