About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

Marvell is empowering the global data economy. Whether at the network core or edge, our leadership technologies make it possible for the world’s data to be processed, moved, stored and secured faster and more reliably. With leading intellectual property and deep system‐level knowledge, Marvell's infrastructure semiconductor solutions are transforming the 5G, cloud computing, enterprise and automotive markets of tomorrow. Marvell Compute and Custom Solutions has been at the forefront of developing and delivering leading edge, high-performance data processing silicon platforms. By delivering a stream of technical innovations through a diverse set of fast-growing product lines, Marvell technology is powering the next-generation data processing and workload acceleration platforms for multiple market segments.

What You Can Expect

• Build and Lead a strong technical team of RTL, DV experts for SoC and own and drive execution of SoC development for large CCS products.

• Work with various stakeholders to define the strategy, requirements for CCS products,

• Lead RTL. DV efforts for blocks, subsystems, and top-level verification.

• Define the sub system architecture, micro-architecture and register specification for highly complex So Cs. Drive and participate in specification

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• Conduct detailed performance, architectural and design requirement reviews with cross-functional teams, IP Vendors and customers

Implement a specification using RTL coding techniques and best practices

• Work with third party vendors to define customization requirements of third party IPs (controller, PHY , etc.)

• Work with the physical design teams, reviewing and providing guidance in floorplanning, power analysis, synthesis and timing signoff.

Work with the verification team on pre-silicon verification tasks such as reviewing the verification test plans, coverage analysis, full-chip simulation and emulation, performance and power analysis and debug

• Help develop and/or evaluate design and verification methodologies and participate in improving existing ones

• Collaborate with and provide guidance to the post silicon and software teams for prototype bring up and performance tuning

• Provide mentorship to the more junior team member

• Develop and maintain UVM-based verification environments.

• Define and review test plans with architecture and design teams

• Verify designs using directed and constrained random techniques.

• Maintain regression, debug failures, and analyze coverage.

• Drive verification to meet coverage targets.

• Contribute to next-gen data processing and hardware accelerator verification.

• Focus on networking domain verification for future solutions.

• Ensure design closure using innovative and automated technique

What We're Looking For

• Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 16+ years of related professional experience or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 12+ years of experience.
• Proven track record of managing technical teams and leading cross-functional teams for design emulation and verification.
• Substantial knowledge of emulation platforms offerings from various vendors such as Synopsys, Cadence, Siemens including extensive experience in building complex SOC emulation models
• Working knowledge in one or more of the following: Processor architecture, SOC components, SOC inter-connect buses, IO protocols (PCIe, CXL, Ethernet) and memory technologies interfaces (DDR, HBM)
• Strong understanding of product development process of large SOCs and verification/debug experience in emulation platforms.
• Strong experience in coding in scripting languages like Perl, Python, Tcl & UNIX Shell etc

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.