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职位Marvell

Hardware & Silicon Validation Senior Staff Engineer

Marvell

Hardware & Silicon Validation Senior Staff Engineer

Marvell

Westborough, MA

·

On-site

·

Full-time

·

3w ago

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

The Custom Cloud Solutions (CCS) Hardware Validation Group is responsible for ensuring the quality, reliability, and performance of next generation data center ASIC and SoC products spanning a diverse portfolio that includes cloud infrastructure, AI accelerators, network processors, NICs, custom ASICs, SSD controllers, CXL devices, and domain specific accelerators.
The team owns end to end hardware validation, working across the product lifecycle from early silicon bring up through system level qualification. Our scope includes functional hardware validation, electrical characterization, high speed SERDES validation, and system/platform validation, all executed in advanced, fully instrumented hardware labs. The group validates complex, high performance silicon and platforms across a wide range of critical technologies and interfaces, including Memory Subsystems (DDR, HBM, memory controllers), High Speed Interconnects (PCIe, Ethernet, CPRI, PAM4/NRZ), D2D interconnects, Storage, and IO (Flash and NVME, SSD controllers, USB) and System and Platform testing.

What You Can Expect:

Marvell is seeking Senior Staff Validation Engineer in the Custom Compute and Storage Business Group to validate Ethernet, PCIe and other high-speed interfaces in post-silicon environment. It encompasses the full development cycle of Marvell state-of-the-art Ser Des development from IP stage to productization into customer application. It involves all aspects of Ser Des engineering including circuitries, DSP algorithm and initialization for electrical performance and compliance.

Key Responsibilities: • As a high speed Ser Des validation Engineer, you will focus on the validation of Ethernet/PCIe/Die-to-Die interface as well as supporting the debug and functional tests of the PHY. You’ll have an opportunity to work on the latest Ethernet 224G, PCIe Gen6/7 technology and product development, along with other advanced high-speed Ser Des.

  • Complete ownership of high speed Ser Des validation in post-silicon environment.
  • Document, execute and report overall PHY validation for Marvell custom silicon devices.
  • Perform lab-based silicon bring-up and Ser Des engineering focused on Ethernet/PCIe/D2D Physical layer functionality.
  • Participate in collaborative discussions to drive resolution for technical issues.
  • Troubleshoot failing tests with diagnostics, hardware analyzers and software tools.
  • Work with cross-functional teams to debug any post-silicon and/or customer issues related to Ser Des PHY.

What We're Looking For:

  • Bachelor’s degree in Electrical Engineering or related fields and 5-7 years of related professional experience OR Master’s degree in Electrical Engineering or related fields with 3-5 years of experience.
  • 3+ years of experience with high-speed IO testing, debugging and validation
  • In depth working knowledge of test equipment used for SERDES characterization (Scope, BERT, Network analyzer etc.).
  • Strong understanding of high-speed Ser Des, equalization technique and Ser Des links and channels.
  • Working knowledge of Ethernet/PCIe interface and characterization.
  • Experience with Python, or other programming language.
  • Critical thinking and problem-solving attitude and ownership of the group’s results.
  • Excellent verbal and written communication skills.
  • Knowledge of the physical and protocol levels (PIPE I/F, PCS, MAC) of one or more common high-speed interfaces is an asset.
  • Knowledge of board design, board schematics and board layout, and signal integrity is a plus.

Expected Base Pay Range (USD)

143,400 - 212,230, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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关于Marvell

Marvell

Marvell

Public

Marvell Technology, Inc. is an American company, headquartered in Santa Clara, California, which develops and produces semiconductors and related technology.

5,001-10,000

员工数

Santa Clara

总部位置

$15.2B

企业估值

评价

3.6

10条评价

工作生活平衡

3.2

薪酬

3.8

企业文化

3.5

职业发展

2.8

管理层

2.9

65%

推荐给朋友

优点

Good benefits and compensation

Supportive team and leadership

Flexible work arrangements

缺点

Limited career advancement opportunities

High workload and long hours

Poor management and communication

薪资范围

16个数据点

Junior/L3

Junior/L3 · DATA SCIENCE AND ENGINEERING PROFESSIONAL II

1份报告

$111,800

年薪总额

基本工资

$86,000

股票

-

奖金

-

$111,800

$111,800

面试经验

1次面试

难度

4.0

/ 5

时长

14-28周

录用率

100%

体验

正面 100%

中性 0%

负面 0%

面试流程

1

Application Review

2

Recruiter Screen

3

Technical Phone Screen

4

Technical Interview

5

Final Round/Onsite

6

Offer

常见问题

Technical Knowledge

System Design

Behavioral/STAR

Past Experience

UI/Frontend Architecture