About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

Built on decades of expertise and execution, Marvell’s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, you’ll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor chips in a leading-edge CMOS process technology, targeted at server, 5G/6G, and networking applications.

What You Can Expect

You will work with both local and global team members on the physical design of complex chips as well as the methodology to enable an efficient and robust design process. This position also provides an exciting platform to engage with diverse engineering challenges within a collaborative and innovative environment at Marvell.
We are hiring for multiple office locations. This is a full-time, on-site role, and employees are expected to work at their designated team location. Relocation assistance is available for qualified candidates.

Key responsibilities include:

• Work with design teams across various disciplines such as Digital/RTL/Analog to ensure design convergence and integration in a timely manner

• Implement/support designs with multi-voltage designs through all aspects of implementation (place and route, static timing, physical verification) using industry standard EDA tools

• Work with RTL design teams to drive assembly and design closure.

• Provide technical direction, coaching, and mentoring to junior employees and colleagues when necessary to achieve successful project outcomes

• Write scripts in Shell, Python, and TCL to extract data and achieve productivity enhancements through automation

What We're Looking For:

• Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience or equivalent professional experience in lieu of a formal degree.

• 5+ years experience in back-end physical design

• Expertise in full-chip & sub-hierarchy integration

• Experience integrating and taping out large designs utilizing a digital design environment.

• Good understanding of RTL to GDS flows and methodology

• Good scripting skills in Perl, tcl and Python

• Good understanding of digital logic and computer architecture

• Knowledge of Verilog

• Good communication skills and self-discipline contributing in a team environment

• Working knowledge of static timing analysis tools such as Tempus or Prime Time and EM/IR-Drop/Crosstalk analysis tools like Voltus or Prime Rail is advantageous

• Working knowledge of physical verification and formal verification tools (e.g., Calibre, LEC, Formality) is advantageous

• Experience with multi-voltage and low-power design techniques is advantageous

• Experience with Cadence Innovus is preferred

Expected Base Pay Range (USD)

125,900 - 186,260, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity

As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, Co Pilot, or note-taking bots) during interviews.
Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.