About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

Marvell’s Central Engineering (CE) organization develops the industry’s most advanced High-Speed Ser Des (HSS) IPs, covering a broad range of applications including cloud data center, AI/ML infrastructure, 5G wireless, automotive, storage, and optical interconnects. Central System Engineering (CSE), a key function within CE, is responsible for validation, characterization, and application engineering support of high-speed Ser Des and analog macros for electrical and optical applications. The team also develops data communication system hardware and software infrastructure to deliver the highest quality Ser Des IP and analog macros across Marvell’s Business Units.

What You Can Expect

In this role, you will serve as the primary technical interface between Marvell's Central Engineering IP team and Marvell’s customers, supporting the full lifecycle of Ser Des IP integration across customized ASIC and switch programs. This is a hybrid position based on the Santa Clara office, with occasional travel to customer sites for silicon bringup and onsite support.

Core responsibilities include:

• Leading Ser Des IP integration and customer bringup support from initial design review through silicon validation and production release, including IP kick-off reviews, risk assessments, package and test board reviews, and test plan alignment with internal BUs and customers

• Coordinating and driving the right engineering resources across IP design, firmware, and validation teams to ensure smooth SoC bringup and stable production

• Diagnosing and resolving signal integrity issues — including equalization, link training, and FEC performance — across multi-data-rate Ser Des and supporting analog IPs (analog bias, clock buffers, process monitors, temperature sensors)

• Supporting high-speed interface applications including Ethernet single-channel (10G/25G/50G/100G/200G KR/CR/C2M/C2C), PCIe Gen1–Gen6, CPRI, JESD, and CEI

• Owning customer technical escalations end-to-end, from root cause analysis through resolution and documentation

• Analyzing signal integrity through PCB layout review, channel simulation, and S-parameter analysis to identify integration risks early in the design cycle

• Utilizing industry-standard high-speed test equipment — including electrical characterization and compliance test tools — to efficiently isolate and debug issues in the lab

• Developing and delivering customer-facing technical collateral including integration guides, application notes, and API documentation

• Presenting program status, technical findings, and recommendations to both customer engineering teams and internal leadership

• Cross-functional collaboration is central to this role. You will work closely with IP design engineers, DSP and firmware teams, and customer engineers and SoC architects, serving as the technical authority that keeps programs moving forward.

What We're Looking For

Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience. OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience.

• Proven experience in high-speed Ser Des IP integration and silicon bringup, with a strong foundation in signal integrity analysis, Ser Des equalization, and end-to-end debug across complex SoC programs.

• Prior work on switch, custom ASIC, or connectivity programs (PCIe, Ethernet, D2D) is highly valued.

• Tthe ability to work independently across multiple customer engagements simultaneously , owning the full technical lifecycle from integration kickoff through production.

• Strong communication skills are essential.

Expected Base Pay Range (USD)

154,680 - 231,700, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.