About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

The Central Engineering ASIC Design Services Team within Marvell provides chip solutions for next generation 5G carriers, cloud data centers, enterprise, and automotive applications. As a manager within the ASIC team, you will have the opportunity to lead an experienced team and growing team of physical design, static timing analysis (STA) and design for test (DFT) engineers. You will also have the opportunity to interact with customers and the worldwide team to develop solutions to meet our customer’s needs.

What You Can Expect

• As a leading member of central physical design team, you will provide backend design service for multiple Marvell SOC design groups, from floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff to physical verification (DRC/LVS/Antenna).
• You will have the opportunity to work on many varieties of challenging designs, i.e. low power and high speed SOCs, and use your expertise to influence frontend and integration team to ensure successful tapeouts.
• Your responsibility may include participating in or leading cutting-edge physical design methodology and flow development.
• Your role may also include project management and leading a team of physical design engineers on project level.
• Lead and mentor a team of engineers, fostering an environment of technical excellence and collaboration.
• Provide strategic technical direction and oversight, ensuring successful execution of design to meet project milestones.
• Act as a key interface between senior leadership and your team, translating high-level objectives into actionable technical and project plans.
• Guide professional development of team members through coaching, training, and performance evaluations to help them advance their careers.
• Champion best practices in IC design methodology, promoting innovation and continuous improvement.

What We're Looking For

• BS/MS in EE/CS with 10+ years of hands-on experience in CAD back-end physical design and verification. Familiar with hierarchical physical design strategies, methodologies and deep sub-micron technology issues line N5/N3/N2. Familiar with ASIC design flow, Verilog HDL, synthesis and timing closure.
• Proven track records of leading chip level backend implementation activity and taping out complex SOC chips under tight schedule pressure.
• In-depth understanding of current design technologies used in major foundries.
• Must be programming-minded, expert on using Makefile/Tcl/Perl to improve efficiency and streamline process.
• Detail oriented, self-motivated team worker, good verbal and written communication skills.
• Must be a power user of Cadence suite (Genus, Innovus) or Synopsys suite (IC Compiler, Fusion complier). .
• Strong knowledge on static timing analysis (Tempus, or Prime Time), EM/IR-Drop/crosstalk analysis (Celtic, PTSI, Apache, Astro Rail, Prime Rail), extraction (QRC, StarRC), formal or physical verification (LEC, Formality, Calibre) a plus.
• Good communication skills, ability to communicate clearly with cross functional teams on deliverables and status

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.